Patents by Inventor Alan Krech

Alan Krech has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913990
    Abstract: An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 27, 2024
    Assignee: Advantest Corporation
    Inventors: Olaf Pöppe, Klaus-Dieter Hilliges, Alan Krech
  • Patent number: 11415628
    Abstract: An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Advantest Corporation
    Inventors: Olaf Pöppe, Klaus-Dieter Hilliges, Alan Krech
  • Publication number: 20210073094
    Abstract: An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 11, 2021
    Inventors: Olaf PÖPPE, Klaus-Dieter HILLIGES, Alan KRECH
  • Publication number: 20210055347
    Abstract: An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Olaf PÖPPE, Klaus-Dieter HILLIGES, Alan KRECH
  • Publication number: 20070195618
    Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.
    Type: Application
    Filed: February 17, 2006
    Publication date: August 23, 2007
    Inventors: Alan Krech, Stephen Jordan, John Freeseman