Patents by Inventor Alan L. Davis
Alan L. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8472802Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted (401) from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.Type: GrantFiled: March 10, 2008Date of Patent: June 25, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jung Ho Ahn, Moray McLaren, Alan L. Davis
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Publication number: 20110069963Abstract: Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.Type: ApplicationFiled: March 11, 2008Publication date: March 24, 2011Inventors: Moray McLaren, Jung Ho Ahn, Nathan L. Binkert, Alan L. Davis, Norman P. Jouppi
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Publication number: 20110020009Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted (401) from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.Type: ApplicationFiled: March 10, 2008Publication date: January 27, 2011Inventors: Jung Ahn Ho, Moray Mclaren, Alan L. Davis
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Patent number: 7103883Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: GrantFiled: May 1, 2001Date of Patent: September 5, 2006Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider
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Patent number: 6889320Abstract: A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses.Type: GrantFiled: October 31, 2000Date of Patent: May 3, 2005Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Richard H. Scales, Natarajan Seshan, Eric J. Stotzer, Reid E. Tatge
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Patent number: 6829759Abstract: A method for generating a translation display includes receiving a source file (414) including a plurality of source elements (422) and a translation file (418) including a plurality of translation elements (426) corresponding to the source elements (422). The source and translation files (414 and 418) are partitioned into a plurality of partitions (458). Each partition (458) has a group of source elements (422) and a group of all translation elements (426) corresponding to the group of source elements (422). The corresponding source and translation groups are aligned for display.Type: GrantFiled: October 28, 1999Date of Patent: December 7, 2004Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Patent number: 6785850Abstract: The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software system (140) is executed on a host processor interconnected with the hardware system (103). A database (152) is accessed to obtain a description of a set of functional components present within the hardware system (103). A software representation (154) of the capabilities of each functional component is created by using the description of the set of functional components. Then, the software representation (154) is interrogated to determine a set of operational capabilities of the hardware system (103). The software system (140) is then operated in a manner that is responsive to the set of operational capabilities of the hardware system (103).Type: GrantFiled: March 2, 2001Date of Patent: August 31, 2004Assignee: Texas Instruments IncorporatedInventors: Jonathan Dzoba, Gary L. Swoboda, Sambandam Manohar, Kenneth E. Aron, Leland J. Szewerenko, Paul Gingrich, Jiuling Liu, Alan L. Davis, Edmund Sim
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Patent number: 6728950Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: GrantFiled: May 1, 2001Date of Patent: April 27, 2004Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Publication number: 20040044874Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.Type: ApplicationFiled: September 2, 2003Publication date: March 4, 2004Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
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Patent number: 6625719Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.Type: GrantFiled: June 14, 2002Date of Patent: September 23, 2003Assignee: Texas Instruments IncorporatedInventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
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Publication number: 20030056081Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.Type: ApplicationFiled: June 14, 2002Publication date: March 20, 2003Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
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Patent number: 6477641Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: GrantFiled: May 1, 2001Date of Patent: November 5, 2002Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Publication number: 20020157084Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: ApplicationFiled: May 1, 2001Publication date: October 24, 2002Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Patent number: 6411984Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.Type: GrantFiled: May 1, 1998Date of Patent: June 25, 2002Assignee: Texas Instruments IncorporatedInventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
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Patent number: 6374346Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.Type: GrantFiled: January 23, 1998Date of Patent: April 16, 2002Assignee: Texas Instruments IncorporatedInventors: Natarajan Seshan, Laurence R. Simar, Jr., Reid E. Tatge, Alan L. Davis
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Publication number: 20010042226Abstract: The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software system (140) is executed on a host processor interconnected with the hardware system (103). A database (152) is accessed to obtain a description of a set of functional components present within the hardware system (103). A software representation (154) of the capabilities of each functional component is created by using the description of the set of functional components. Then, the software representation (154) is interrogated to determine a set of operational capabilities of the hardware system (103). The software system (140) is then operated in a manner that is responsive to the set of operational capabilities of the hardware system (103).Type: ApplicationFiled: March 2, 2001Publication date: November 15, 2001Inventors: Jonathan Dzoba, Gary L. Swoboda, Sambandam Manohar, Kenneth E. Aron, Leland J. Szewerenko, Paul Gingrich, Jiuling Liu, Alan L. Davis, Edmund Sim
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Publication number: 20010018764Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: ApplicationFiled: May 1, 2001Publication date: August 30, 2001Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Publication number: 20010016941Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: ApplicationFiled: May 1, 2001Publication date: August 23, 2001Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Publication number: 20010016940Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.Type: ApplicationFiled: May 1, 2001Publication date: August 23, 2001Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider, Raj Kanagasabai
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Patent number: 6002876Abstract: A method of producing a computer program for a computer capable of operating in a plurality of disjoint instruction sets. The method produces a plurality of independently callable functions. For each function the method determines a target instruction set employed by the function. The method provides the function with a name corresponding to the target instruction set. The function name is preferably a modification of a user provided function name corresponding to the target instruction set. The method identifies each call of another independent function and provides each with a name corresponding to the target instruction set. The method produces a veneer function for each function and for each other instruction set. The veneer functions include changing the computer from operating in the other instruction set to operating in the target instruction set, calling the corresponding function, changing the computer to operate in the other instruction set, and a return command.Type: GrantFiled: September 26, 1997Date of Patent: December 14, 1999Assignee: Texas Instruments IncorporatedInventors: Alan L. Davis, Jonathan F. Humphreys, Reid E. Tatge