Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made.

Abstract: An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

Abstract: A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files.

Abstract: A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.