Abstract: Methods are presented to monitor the performance of an ion implanter such as the E500. Ion implantation typically involves physical processes performed on a wafer such as rotation, tilt, and twist. These methods generate particulate contaminants (PCs) that affect the kill rate of the semiconductor devices on the wafer. Variations in tilt angle also compromise dose accuracy. Presently, methods for testing for PCs and implant dose accuracy do not simulate actual manufacturing conditions. This invention discloses methods to test PC buildup using multiple wafers that are subjected to rotation, twist, tilt, and combinations thereof. Additionally, methods to test dose accuracy are presented, involving implanting a monitor wafer at an angle where the crystalline channel is aligned with the ion beam. Measuring sheet resistance as a function of tilt angle at this point ensures accurate tilt-angle calibration of the ion implanter.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.