Patents by Inventor Alan L. Roberts
Alan L. Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6965503Abstract: An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).Type: GrantFiled: September 30, 2003Date of Patent: November 15, 2005Assignee: International Business Machines CorporationInventors: John Connor, Robert J. Gauthier, Jr., Christopher S. Putnam, Alan L. Roberts
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Patent number: 6396336Abstract: The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage.Type: GrantFiled: June 15, 2001Date of Patent: May 28, 2002Assignee: International Business Machines CorporationInventors: Alan L. Roberts, Reid A. Wistort
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Patent number: 6356981Abstract: An apparatus and method are provided that preserve data coherency within a DDR SRAM without sacrificing SRAM performance. The presence of a read-following-double-write (RFDW) condition is detected and data is prevented from being output from the SRAM following detection of the RFDW condition until coherent data is available. To detect an RFDW condition, preferably a double write signal is detected during a double write operation, and the double write signal is latched. A read signal also is detected during a read operation and the latched double write signal is compared to the read signal. If both the latched double write signal and the read signal are in a logic state that indicates that each is being performed, the RFDW condition is deemed detected. To prevent data from being pre-maturely output from the SRAM, the off chip driver circuitry of the SRAM preferably is maintained in a tri-state condition and data within a write buffer of the SRAM preferably is blocked until coherent data is available.Type: GrantFiled: February 12, 1999Date of Patent: March 12, 2002Assignee: International Business Machines CorporationInventors: Alan L. Roberts, Reid A. Wistort
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Patent number: 6333671Abstract: The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage.Type: GrantFiled: November 3, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Alan L. Roberts, Reid A. Wistort
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Publication number: 20010028270Abstract: The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage.Type: ApplicationFiled: June 15, 2001Publication date: October 11, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORORATIONInventors: Alan L. Roberts, Reid A. Wistort
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Patent number: 6262911Abstract: A method to statically balance Silicon-On-Insulator (SOI) parasitic effects is disclosed. Additionally, eight device Static Random Access Memory (SRAM) cells using the method are provided. A balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage, is provided. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times.Type: GrantFiled: June 22, 2000Date of Patent: July 17, 2001Assignee: International Business Machines CorporationInventors: Geordie Braceras, William F. Pokorny, Alan L. Roberts
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Patent number: 5841720Abstract: A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.Type: GrantFiled: August 26, 1997Date of Patent: November 24, 1998Assignee: International Business Machines CorporationInventors: James J. Covino, Alan L. Roberts, Jose R. Sousa
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Patent number: 5721957Abstract: A method and data processing system are disclosed for storing data in a cache memory and retrieving data from a cache memory in a selected one of multiple data formats. According to the present invention, bits are selected from an L-byte data word to produce N input words, which each have m bits. The N input words are then stored within the cache memory. In response to receipt of a request for data within the L-byte data word having a selected one of the multiple data formats, the N input words are recalled from the cache memory and simultaneously formatted to produce a P-byte formatted data word. Thus, a P-byte formatted data word is efficiently retrieved from the cache memory and formatted according to a selected one of multiple data formats before being utilized in the data processing system.Type: GrantFiled: June 3, 1996Date of Patent: February 24, 1998Assignee: International Business Machines CorporationInventors: Lawrence P. Huang, David M. Svetlecic, Donald A. Evans, Alan L. Roberts
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Patent number: 5563833Abstract: An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.Type: GrantFiled: March 3, 1995Date of Patent: October 8, 1996Assignee: International Business Machines CorporationInventors: Robert D. Adams, John Connor, James J. Covino, Roy C. Flaker, Garrett S. Koch, Alan L. Roberts, Jose R. Sousa, Luigi Ternullo, Jr.
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Patent number: 5561781Abstract: A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.Type: GrantFiled: January 23, 1995Date of Patent: October 1, 1996Assignee: International Business Machines CorporationInventors: George M. Braceras, Alan L. Roberts