Patents by Inventor Alan L. Westwick

Alan L. Westwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180375325
    Abstract: A switch controls current to be supplied to an inductive load when turned on. A clamp circuit clamps a flyback voltage resulting from turning off the switch. The clamp circuit has a first clamping voltage responsive to the switch being turned off, and has a second clamping voltage, higher than the first clamping voltage, responsive to a current level through the inductive load being lower than a predetermined current level. That ensures that as the current comes down to levels required to break contact, the clamp voltage is increased to speed the collapse of the magnetic field when needed to minimize contact wear by maintaining armature momentum.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 27, 2018
    Inventors: Sean A. Lofthouse, Alan L. Westwick
  • Patent number: 9710031
    Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 18, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Thomas S. David
  • Patent number: 9641186
    Abstract: Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: May 2, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Alan L. Westwick
  • Publication number: 20160359495
    Abstract: Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.
    Type: Application
    Filed: June 6, 2015
    Publication date: December 8, 2016
    Inventors: Axel Thomsen, Alan L. Westwick, Ricky Setiawan, Rex Wong Tak Ying
  • Publication number: 20160359497
    Abstract: Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.
    Type: Application
    Filed: June 6, 2015
    Publication date: December 8, 2016
    Inventors: Axel Thomsen, Alan L. Westwick
  • Publication number: 20160359496
    Abstract: Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
    Type: Application
    Filed: June 6, 2015
    Publication date: December 8, 2016
    Inventors: Axel Thomsen, Alan L. Westwick, Ricky Setiawan, Rex Wong Tak Ying
  • Patent number: 9515671
    Abstract: Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: December 6, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Alan L. Westwick, Ricky Setiawan, Rex Wong Tak Ying
  • Patent number: 9503113
    Abstract: Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Alan L. Westwick, Ricky Setiawan, Rex Wong Tak Ying
  • Patent number: 8825921
    Abstract: A technique includes executing at least one instruction on a processor to control a driver circuit; and in response to a predetermined trigger condition, asynchronously causing the driver circuit to enter a predetermined state.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 2, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Thomas S. David
  • Publication number: 20130221940
    Abstract: A technique includes using a pass device of a linear regulator to provide an output signal for the linear regulator in response to a signal that is received at a control terminal of the pass device. The control terminal is coupled to a node, and the node is associated with a bias current. The technique includes using a feedback path to communicate a feedback current with the node to regulate the output signal. The use of the feedback path includes regulating a magnitude of the feedback current to be within a range of magnitudes, which include a magnitude that exceeds a magnitude of the bias current.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Inventors: Shouli Yan, Dazhi Wei, Alan L. Westwick
  • Patent number: 8378724
    Abstract: An apparatus includes a frequency locked loop and a controller. The controller stores a state of the frequency locked loop at which an output signal of the frequency locked loop is locked onto a reference signal and subsequently initializes the frequency locked loop with the stored state to cause the frequency locked loop to relock the output signal to the reference signal.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Thomas S. David, Kenneth W. Fernald, Alan L. Westwick
  • Publication number: 20120173787
    Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Inventors: Alan L. Westwick, Thomas S. David
  • Publication number: 20120166859
    Abstract: An apparatus includes a processor, a clock recovery circuit and a frequency locked loop. The processor receives a system clock signal to clock operations of the processor; and the clock recovery circuit recovers a clock signal from data communication occurring over a bus. The frequency locked loop receives the clock signal from the clock recovery circuit as a reference clock signal, and the frequency locked loop is adapted to lock onto the clock signal provided by the clock recovery circuit to provide the system clock signal.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Kenneth W. Fernald, Thomas S. David, Alan L. Westwick
  • Publication number: 20120165960
    Abstract: A technique includes executing at least one instruction on a processor to control a driver circuit; and in response to a predetermined trigger condition, asynchronously causing the driver circuit to enter a predetermined state.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Alan L. Westwick, Thomas S. David
  • Publication number: 20120161835
    Abstract: An apparatus includes a frequency locked loop and a controller. The controller stores a state of the frequency locked loop at which an output signal of the frequency locked loop is locked onto a reference signal and subsequently initializes the frequency locked loop with the stored state to cause the frequency locked loop to relock the output signal to the reference signal.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Thomas S. David, Kenneth W. Fernald, Alan L. Westwick
  • Patent number: 8149062
    Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 3, 2012
    Assignee: Black Sand Technologies, Inc.
    Inventors: Susanne A. Paul, Alan L. Westwick, Timothy J. Dupuis
  • Patent number: 7908500
    Abstract: A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: March 15, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Donelson A. Shannon, Dazhi Wei, Xiaoling Guo, Gabriel Vogel
  • Patent number: 7873854
    Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: January 18, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Dazhi Wei, Xiaoling Guo, Jia-Hau Liu
  • Patent number: 7873856
    Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 18, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Dazhi Wei, Xiaoling Guo, Jia-Hau Liu
  • Patent number: 7852061
    Abstract: An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: December 14, 2010
    Assignee: Silicon Laboratories Inc.
    Inventors: Jia-Hau Liu, Alan L. Westwick, Douglas S. Piasecki