Patents by Inventor Alan Lee Holesovsky

Alan Lee Holesovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for layout versus schematic validation of integrated circuit designs
    Patent number: 7480878
    Abstract: A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some embodiments the IC layer of interest may include only metal. A layout versus schematic (LVS) comparison is performed using the edited rundeck and an error report is generated.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: January 20, 2009
    Assignee: LSI Logic Corportion
    Inventors: Alan Lee Holesovsky, Viswanathan Lakshmanan, Brent Wray Acott