Patents by Inventor Alan Lee Varner

Alan Lee Varner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9948242
    Abstract: A selectable current limiter circuit to limit the current an amplifier with a load. The limiter circuit limits the current of an amplifier by comparing a voltage reference that follows the output swing of the amplifier to voltage drop across a current limiting resistor coupled to the output of the amplifier. The limiter circuits are operatively coupled to buffer and switch circuits that delay the current limiting until the limiter circuits are activated.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 17, 2018
    Assignee: APEX MICROTECHNOLOGY, INC.
    Inventors: Alan Lee Varner, Gregory Michael Patchin, Kirby Neil Gaulin
  • Publication number: 20180041171
    Abstract: A selectable current limiter circuit. An apparatus and method of limiting the current of amplifiers.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Alan Lee VARNER, Gregory Michael PATCHIN, Kirby Neil GAULIN
  • Patent number: 6914486
    Abstract: Systems and methods to improve bias matching (e.g., for a current feedback amplifier) are described. A compensation signal is combined with one or more bias signals to mitigate mismatch between the bias signals. The compensation signal is generated to correspond to the mismatch between the bias signals. This approach can be implemented to improve performance of an associated amplifier, such as by reducing offset at an input of a portion of the amplifier (e.g., an input buffer) that is biased by the bias signals.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: July 5, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Lee Varner, Paul Damitio
  • Patent number: 6870426
    Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Ahmad Dashtestani, Joel Martin Halbert, Alan Lee Varner
  • Publication number: 20040263252
    Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventors: Ahmad Dashtestani, Joel Martin Halbert, Alan Lee Varner
  • Patent number: 6724260
    Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Lee Varner, Ahmad Dashtestani, Joel M. Halbert, Michael A. Steffes