Abstract: A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal and is stored, and a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal is provided.

Abstract: A System-on-Chip may include initiators, targets exchanging information with the initiators, and a control module. The control module may be configured to selectively set to one of different reduced power consumption modes each of the initiators and each of the targets based upon external reduced power consumption instructions, and selectively wake-up from the reduced power consumption mode each initiator and each target.

Abstract: A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal and is stored, and a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal is provided.

Abstract: An integrated circuit for recovering a position and clock period from an input bi-phase encoded digital signal, such as an SPDIF signal, has a longest interval detector arranged to count the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal. A store arranged to store the longest interval between phase changes and an output provides a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal. The longest interval detector includes a pair of counters for even and odd phase transitions and counts in multiple intervals such that a clock period of 2 UI can be recovered directly from the longest pulse of 6 UI present in the preamble X of an SPDIF signal.

Abstract: An integrated circuit for recovering a position and clock period from an input bi-phase encoded digital signal, such as an SPDIF signal, has a longest interval detector arranged to count the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal. A store arranged to store the longest interval between phase changes and an output provides a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal. The longest interval detector includes a pair of counters for even and odd phase transitions and counts in multiple intervals such that a clock period of 2UI can be recovered directly from the longest pulse of 6UI present in the preamble X of an SPDIF signal.

Abstract: The invention provides methods and compositions for modulating the sensitivity of cells to cytotoxic compounds and other active agents. In accordance with the invention, compositions are provided comprising combinations of ectophosphatase inhibitors and active agents. Active agents include antibiotics, fungicides, herbicides, insecticides, chemotherapeutic agents, and plant growth regulators. By increasing the efficacy of active agents, the invention allows use of compositions with lowered concentrations of active ingredients.

Abstract: The present invention relates to methods for modulating the resistance of cells to foreign compounds, i.e. drugs, antibiotics, etc by altering the ATP gradient across biological membranes. The altering of the ATP gradient across biological membranes is achieved through the manipulation of ecto-phosphatase activity and ABC transporter molecule activity which may be useful to confer herbicide resistance to plants, confer antibiotic resistance to bacteria, confer drug resistance to yeast cells, or to reduce resistance in cells to facilitate chemotherapeutic treatments, and to reduce resistance in bacteria and yeast. The present invention is also directed to the methods for identifying ecto-phosphatase inhibitors and uses thereof.

Abstract: A directory system for providing directory services in a communications network, including a plurality of memory segments for storing respective subsets of directory data for each directory object. The memory segments include attribute segments, object segments, and directory information tree (DIT) segments for respectively storing attribute, management, and hierarchical structure data for directory objects. The directory system monitors usage of directory data stored in the memory segments and redistributes at least a portion of the directory data in the memory segments based on the observed usage to improve the performance of directory services. The directory system also provides transactional messaging services to users.

Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.

Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.