Patents by Inventor Alan Lytle

Alan Lytle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10968113
    Abstract: The invention relates to a device and method to quantify the lead exposure of an aqueous feed to humans, remove lead from the aqueous feed, and identify the presence of lead service lines. The device includes an inlet to receive a lead-containing aqueous feed; an outlet to discharge a lead-depleted treated aqueous feed; and at least one cartridge containing sampling media positioned so that the lead-containing aqueous feed passes from the inlet and through the cartridge to produce the lead-depleted treated aqueous feed for discharge through the outlet.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 6, 2021
    Assignee: GOVERNMENT OF THE UNITED STATES AS REPRESENTED BY THE ADMINISTRATOR OF THE U.S. ENVIRONMENTAL PROTECTION AGENCY
    Inventors: Darren Alan Lytle, Michael Reed Schock
  • Patent number: 10665596
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 10134746
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 9640539
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 2, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 9245894
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Publication number: 20120108068
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 3, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 8029674
    Abstract: A process for treatment of water to convert ammonia to nitrate including: feeding water containing dissolved ammonia, as an influent introducing water to be treated, into a packed column containing filter media as packing; introducing air through a diffuser at the bottom of the packed column to maintain the water saturated with oxygen throughout the packed column; establishing colonies of bacteria converting ammonia to nitrate within the column; and removing an ammonia-free and nitrite-fee effluent from the column.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 4, 2011
    Assignee: The United States of America as represented by the Administrator of the Environmental Protection Agency
    Inventor: Darren Alan Lytle
  • Patent number: 7160799
    Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: January 9, 2007
    Assignee: Agere Systems Inc.
    Inventors: Steven Alan Lytle, Thomas Michael Wolf, Allen Yen
  • Patent number: 6879046
    Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: April 12, 2005
    Assignee: Agere Systems Inc.
    Inventors: Gerald W Gibson, Jr., Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 6550841
    Abstract: A tailgate bed extender for a vehicle truck bed. The tailgate bed extender has a tray mounted on a vehicle tailgate and a rear frame pivotally coupled to the tray. Sidearms are pivotally coupled to opposing side edges of the rear frame and are attachable to the vehicle truck bed. A hinge assembly that has a rotation axis, which is movable relative to the tray, joins the rear frame to the tray. The tailgate bed extender is rotatable from a stored position in which the rear frame abuts the tray to a loading position in which the rear frame is at an angle of approximately 270 degrees to the tray.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: April 22, 2003
    Assignee: Canada Inc.
    Inventors: Peter M. Burdon, Alan Lytle, Peter Oliver, Ruth Lytle
  • Publication number: 20030003765
    Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.
    Type: Application
    Filed: January 2, 2002
    Publication date: January 2, 2003
    Inventors: Gerald W. Gibson, Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 6362638
    Abstract: A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: March 26, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Robert Alan Ashton, Steven Alan Lytle, Mary Drummond Roby, Daniel Joseph Vitkavage
  • Patent number: 6329281
    Abstract: The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: December 11, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Steven Alan Lytle, Mary Drummond Roby, Daniel Joseph Vitkavage
  • Patent number: 5891784
    Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: April 6, 1999
    Assignee: Lucent Technologies, Inc.
    Inventors: Wan Yee Cheung, Sailesh Chittipeddi, Chong-Cheng Fu, Taeho Kook, Avinoam Kornblit, Steven Alan Lytle, Kurt George Steiner, Tungsheng Yang
  • Patent number: 5712176
    Abstract: A process for forming a P.sub.2 O.sub.5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: January 27, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Steven Alan Lytle, Yaw Samuel Obeng, Eric John Persson
  • Patent number: D691872
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 22, 2013
    Assignee: Foundations Worldwide, Inc.
    Inventor: Alan Lytle