Patents by Inventor Alan M. Frost

Alan M. Frost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9946720
    Abstract: Approaches for searching for key terms in a plurality of files include associating a respective key map with each file of the plurality of files in memory of a server. Each key map includes a plurality of bit values and each bit value indicates for a key term whether or not the key term is present in the associated file. The server inputs a search map, and the search map includes a plurality of bit values. Each bit value in the search map indicates for a key term whether or not the key term is a key term to search. The server determines for each key map, whether or not the key map satisfies the search map. Data indicating each file of the plurality of files having an associated key map that satisfies the search map is output by the server.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 17, 2018
    Assignee: IONU SECURITY, INC.
    Inventors: David W. Bennett, Timothy E. Beres, Alan M. Frost
  • Patent number: 9900300
    Abstract: In an approach for protecting against use of clones of electronic devices, a first sequence value is initialized on the server and an equal second sequence value is initialized on an electronic device. In response to a first login request to the server from a user operating the electronic device, the first and second sequence values are compared. If the values are equal, processing of the login process continues. Otherwise, the login request is rejected. If the login is successful, a next value is computed for the first and second sequence values, and the next first and second sequence values are stored on the server and on the electronic device, respectively.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 20, 2018
    Assignee: IONU Security, Inc.
    Inventors: David W. Bennett, Alan M. Frost
  • Patent number: 9773118
    Abstract: Approaches for deduplicating data include generating a first key from plain text data of a first data element. The first data element is encrypted using the first key. The first key is compared to each key of a plurality of previously stored keys, which are associated with other encrypted data elements. In response to the first key matching a second key of the plurality of previously stored keys, the encrypted first data element is compared to the other encrypted data element associated with the second key. In response to the encrypted first data element matching the other encrypted data element, the first key is associated with the other encrypted data element, and the encrypted first data element is discarded.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 26, 2017
    Assignee: IONU Security, Inc.
    Inventors: David W. Bennett, Alan M. Frost
  • Patent number: 9641328
    Abstract: Methods and systems are disclosed for generating a public-private key pair. A programmed processor displays a plurality of questions and inputs two or more answers to two or more of the plurality of questions in response to user input. The processor computes the public-private key pair as a function of the two or more answers to the two or more questions and stores the public-private key pair in memory coupled to the processor.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 2, 2017
    Assignee: IOnU Security, Inc.
    Inventors: David W. Bennett, Alan M. Frost
  • Patent number: 9529946
    Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 27, 2016
    Assignee: XILINX, INC.
    Inventors: Paul R. Schumacher, Graham F. Schelle, Patrick Lysaght, Alan M. Frost
  • Patent number: 9268898
    Abstract: Estimating power consumption of a circuit design includes associating, using a processor, each partition of a plurality of partitions of a circuit design with a probability distribution (315). For each partition, the associated probability distribution specifies a distribution for a probability distribution parameter correlated with power consumption for the partition. Using the processor, an output probability distribution specifying power consumption of the circuit design can be calculated according to the probability distribution of each partition of the circuit design (320).
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 23, 2016
    Assignee: XILINX, INC.
    Inventors: Alan M. Frost, Matthew H. Klein
  • Patent number: 9148032
    Abstract: Approaches for estimating power consumption of an electronic circuit from values of configuration parameters. A user is prompted for values of a first subset of the configuration parameters in a first user interface window that is separate from a second user interface window that provides default values of a second subset of the configuration parameters. An estimated level of power consumption of the electronic circuit is determined by a computer as a function of the user-entered values of the first subset of parameters and the default values of the second subset of parameters. The estimated level of power consumption, the user-entered values of the first subset of parameters, and the default values of the second subset of parameters are simultaneously displayed in a third user interface window. The values of both the first subset and second subset of parameters are editable in the third user interface window.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Alan M. Frost, Smitha Sundaresan
  • Patent number: 8694939
    Abstract: A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 8, 2014
    Assignee: Xilinx, Inc.
    Inventors: Alan M. Frost, Matthew H. Klein, Ronald L. Cline
  • Patent number: 8495538
    Abstract: Approaches for estimating power consumption of a circuit based on a circuit design. For one or more modules of the design, data are input that indicate measured power consumption and circuit resources used by the one or more modules. For one or more other parts of the design, values of parameters are input that specify an operating speed and a resource count. Process-corner, voltage, and temperature values are input. An estimated level of power consumption is determined as a function of the measured power consumption, the values of the parameters, and the values of the process-corner, voltage, and temperature. Data indicative of the estimated level of power consumption are output.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: July 23, 2013
    Assignee: Xilinx, Inc.
    Inventors: Alan M. Frost, Paul R. Schumacher, Timothy J. Burke
  • Patent number: 6581186
    Abstract: Methods and systems are provided in which logic cores from different third party core providers can be integrated for use with a single logic core generator. Core information from the various core providers is collected and formatted into a format that can be utilized by the single logic core generator. The information that is collected comprises at least one, and typically a number of different files. In some embodiments, the relevant core information is captured through the use of a graphical user interface (GUI) that guides particular core providers through a series of dialogs that capture the information. A formatting computer then takes the information and formats it into a form that can be utilized by the particular logic core generator. In the described embodiment, the information is formatted into at least one XCD file, which can then be utilized by the logic core generator. The newly-formatted cores can then be distributed to particular users for use with the core generator.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: June 17, 2003
    Assignee: Xilinx, Inc.
    Inventors: Alan M. Frost, Smitha Sundaresan, James L. Burnham