Abstract: A management controller, method and program product for forcing one or more power states on a display, the management controller comprising: a computer (110) configured to receive a power management electronic signal; the computer (110) comprising control logic that operates without use of an operating system to determine a desired level of the power management electronic signal and to set the power management electronic signal to the desired level; and the computer (110) configured to send the power management electronic signal at the desired level to a monitor (120).

Abstract: Dynamically managing power consumption in a computer system having at least two parallel power converters in order to improve efficiency. A maximum power capacity for each of the power converters is determined and then power consumption of the computer system is monitored. If the power consumption of the computer system can be provided by less than all of the parallel power converters then one or more of the power converters is turned off, such that a reduced number of parallel power converters remains turned on. A reduced maximum power capacity of the reduced number of parallel power converters is determined and a power cap value is set for the computer system that is less than or equal to the reduced maximum power capacity. The computer system is throttled at the power cap to prevent power consumption of the computer system from exceeding the power cap value.

Abstract: A management controller, method and program product for forcing one or more power states on a display, the management controller comprising: a computer (110) configured to receive a power management electronic signal; the computer (110) comprising control logic that operates without use of an operating system to determine a desired level of the power management electronic signal and to set the power management electronic signal to the desired level; and the computer (110) configured to send the power management electronic signal at the desired level to a monitor (120).

Abstract: A method for phase shedding is disclosed. The method comprises the following steps. At step one power is supplied to a memory sub-system with a multi-phase regulator wherein a maximum number of phases in the multi-phase regulator are enabled. At step two the memory configuration of the memory sub-system is determined. At step three at least one of the phases of the multi-phase regulator is disabled when the memory configuration meets a predetermined criteria.

Abstract: Dynamically managing power consumption in a computer system having at least two parallel power converters in order to improve efficiency. A maximum power capacity for each of the power converters is determined and then power consumption of the computer system is monitored. If the power consumption of the computer system can be provided by less than all of the parallel power converters then one or more of the power converters is turned off, such that a reduced number of parallel power converters remains turned on. A reduced maximum power capacity of the reduced number of parallel power converters is determined and a power cap value is set for the computer system that is less than or equal to the reduced maximum power capacity. The computer system is throttled at the power cap to prevent power consumption of the computer system from exceeding the power cap value.

Abstract: A computer system powers off upon operation of a power switch when the power switch is enabled. A switch mask enables and disables the power switch without intervention by an operating system of the computer system.

Abstract: A method and apparatus may be provided to allow for the enablement or disablement of a computer remotely for servicing or other reasons. The computer may be enabled remotely by one or more circuits that may simulate a system switch turn on or turn off event.

Abstract: A battery-powered computer chassis intrusion detection circuit which stores the time and date that the chassis hood, components, or AC power was removed. When intrusion occurs, an alarm bit isolates the detection circuit oscillator from the circuit, effectively stopping a real time clock from incrementing the time and date. When the computer is powered back up, internal ROM checks to see if an alarm condition occurred. If so, the intrusion date and time is recorded and the user or administrator may be alerted.

Abstract: A method and apparatus may be provided to allow for the enablement or disablement of a computer remotely for servicing or other reasons. The computer may be enabled remotely by one or more circuits that may simulate a system switch turn on or turn off event.

Abstract: A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.

Abstract: A battery-powered computer chassis intrusion detection circuit which stores the time and date that the chassis hood, components, or AC power was removed. When intrusion occurs, an alarm bit isolates the detection circuit oscillator from the circuit, effectively stopping a real time clock from incrementing the time and date. When the computer is powered back up, internal ROM checks to see if an alarm condition occurred. If so, the intrusion date and time is recorded and the user or administrator may be alerted.

Abstract: A battery-powered computer chassis intrusion detection circuit which stores the time and date that the chassis hood, components, or AC power was removed. When intrusion occurs, an alarm bit isolates the detection circuit oscillator from the circuit, effectively stopping a real time clock from incrementing the time and date. When the computer is powered back up, internal ROM checks to see if an alarm condition occurred. If so, the intrusion date and time is recorded and the user or administrator may be alerted.