Patents by Inventor Alan McKee

Alan McKee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7370209
    Abstract: Disclosed are systems and methods for increasing the difficulty of data sniffing. In one embodiment, a system and a method pertain to presenting information to a user via an output device, the information corresponding to characters available for identification as part of sensitive information to be entered by the user, receiving from the user via an input device identification of information other than the explicit sensitive information, the received information being indicative of the sensitive information, such that the sensitive information cannot be captured directly from the user identification through data sniffing, and interpreting the identified information to determine the sensitive information.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: May 6, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Blaine Douglas Gaither, Bret Alan McKee
  • Publication number: 20050120892
    Abstract: The invention relates to a utensil which prepares the surface for food items prior to cooking. A utensil for the preparation of food items comprising a first part (5) defining a container for receiving in use food items through an opening of the first part (5) and means (6) for closing the opening of the first part wherein at least a portion of an inner surface of the first part (5) comprises protrusions (4) which said food items may be brought into contact with, in use, by shaking the utensil so as to roughen or abrade surfaces of said food items.
    Type: Application
    Filed: January 23, 2003
    Publication date: June 9, 2005
    Inventor: Alan McKee
  • Publication number: 20040153660
    Abstract: Disclosed are systems and methods for increasing the difficulty of data sniffing. In one embodiment, a system and a method pertain to presenting information to a user via an output device, the information corresponding to characters available for identification as part of sensitive information to be entered by the user, receiving from the user via an input device identification of information other than the explicit sensitive information, the received information being indicative of the sensitive information, such that the sensitive information cannot be captured directly from the user identification through data sniffing, and interpreting the identified information to determine the sensitive information.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Inventors: Blaine Douglas Gaither, Bret Alan McKee
  • Patent number: 6136700
    Abstract: A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Peter S. McAnally, Jeffrey Alan McKee, Dirk Noel Anderson
  • Patent number: 5972769
    Abstract: A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: October 26, 1999
    Assignee: Texas Instruments Incoporated
    Inventors: Robert Yung-Hsi Tsu, Jing Shu, Isamu Asano, Jeffrey Alan McKee
  • Patent number: 5909628
    Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: June 1, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali, Keith A. Joyner, Yin Hu, Jeffrey Alan McKee, Peter Stewart McAnally
  • Patent number: 5804088
    Abstract: An isotropic or partially isotropic etch shrinks lithographically patterned photoresist (211, 212) to yield reduced linewidth patterned photoresist (213, 214) with a buried antireflective coating also acting as an etchstop or a sacrificial layer. The reduced linewidth pattern (213, 214) provide an etch mask for subsequent anisotropic etching of underlying material such as polysilicon (206) or metal or insulator or ferroelectric.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: September 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey Alan McKee