Abstract: A droplet deposition apparatus (1) comprising: a first head module (101A, 101B, 102A) and a second head module (101B, 102A, 102B) arranged in at least partially overlapping relationship, each head module having a plurality of nozzles in at least one nozzle array (A1, B1); and a storage (200) configured to store a table of determined best aligned nozzle pairs in an overlap region and corresponding skew angles (?i) of at least one of the head modules relative to a datum of the droplet deposition apparatus and/or a corresponding positional offset of the second head module relative to the first head module; wherein, in the overlap region, nozzles of the first head module are arranged at a first nozzle pitch (P2) and nozzles of the second head module are arranged at a second nozzle itch (P3).

Abstract: A droplet deposition apparatus (1) comprising: a first head module (101A, 101B, 102A) and a second head module (101B, 102A, 102B) arranged in at least partially overlapping relationship, each head module having a plurality of nozzles in at least one nozzle array (A1, B1); and a storage (200) configured to store a table of determined best aligned nozzle pairs in an overlap region and corresponding skew angles (?i) of at least one of the head modules relative to a datum of the droplet deposition apparatus and/or a corresponding positional offset of the second head module relative to the first head module; wherein, in the overlap region, nozzles of the first head module are arranged at a first nozzle pitch (P2) and nozzles of the second head module are arranged at a second nozzle itch (P3).

Abstract: A method for quantitatively evaluating multiple computer-based plate tectonic models for application in a geographic region of interest, in some embodiments, comprises: selecting a plurality of computer-based plate tectonic models; using multiple computer-based plate tectonic models to generate one or more predictions for one or more geological parameters; obtaining observational data for each of said one or more geological parameters; for each of said one or more geological parameters, quantitatively comparing the predictions and the observational data to determine model rankings; and displaying said model rankings on a computer display.

Abstract: A method for quantitatively evaluating multiple computer-based plate tectonic models for application in a geographic region of interest, in some embodiments, comprises: selecting a plurality of computer-based plate tectonic models; using multiple computer-based plate tectonic models to generate one or more predictions for one or more geological parameters; obtaining observational data for each of said one or more geological parameters; for each of said one or more geological parameters, quantitatively comparing the predictions and the observational data to determine model rankings; and displaying said model rankings on a computer display.

Abstract: A method for quantitatively evaluating multiple computer-based plate tectonic models for application in a geographic region of interest, in some embodiments, comprises: selecting a plurality of computer-based plate tectonic models; using multiple computer-based plate tectonic models to generate one or more predictions for one or more geological parameters; obtaining observational data for each of said one or more geological parameters; for each of said one or more geological parameters, quantitatively comparing the predictions and the observational data to determine model rankings; and displaying said model rankings on a computer display.

Abstract: A method for quantitatively evaluating multiple computer-based plate tectonic models for application in a geographic region of interest, in some embodiments, comprises: selecting a plurality of computer-based plate tectonic models; using multiple computer-based plate tectonic models to generate one or more predictions for one or more geological parameters; obtaining observational data for each of said one or more geological parameters; for each of said one or more geological parameters, quantitatively comparing the predictions and the observational data to determine model rankings; and displaying said model rankings on a computer display.

Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.

Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.

Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.

Abstract: The present invention relates to a crossword puzzle game. The game includes a medium. The game includes indicia displayed on the medium and representing a crossword portion having a plurality of adjacent cells for filling in intersecting words. The crossword portion has at least one clue for supplying at least one of the words. The game includes indicia displayed on the medium and representing a graphical puzzle portion the solution to which supplies another of the words, whereby solving the graphical puzzle portion promotes solving the crossword portion and, alternatively, solving the crossword portion promotes solving the graphical puzzle portion.

Abstract: Debit or credit card transaction data includes one or a combination of digital card data read from a debit or credit card, transaction amount, shop identification information, and personal identification information like PIN numbers. This card transaction 5 data is in digital form. Where sales are performed on-the-go, it is now necessary to contact the card data center manually to obtain necessary information, for example approval code for the sales. Although it seems straight forward to send the digital card data over a mobile phone to resolve this issue, this approach has various problems including lack of support of all mobile 10 phones for data communication, expensive subscription fee to data plan is required, and unbounded delay in the transaction time. The current invention provides a method for performing debit or credit card transactions over mobile phone networks.

Abstract: A semiconductor device includes an integrated main circuit and an auxiliary circuit on a semiconductor substrate. The auxiliary circuit is configured to output and/or for receive electrical signals to and/or from the main circuit and is arranged at a distance from the main circuit in a kerf region of the semiconductor device. The main and auxiliary circuits each include a contact device that can be externally contact-connected to produce a temporary electrical signal connection between the main and auxiliary circuits.

Abstract: The specific application initially contemplated for the V-RAD invention is that of feed rate control of liquid chemical solutions for the purpose of municipal and industrial water treatment. In this application, a vacuum solution feed system is commonly operated by water forced through a Venturi nozzle to create a vacuum that is used to draw the liquid chemical solution into the water. In the prior art, feed rate control has been achieved by employing a variable area orifice control valve. However, in the application of liquid chemical solution injection for industrial and municipal water treatment, the variable area orifice concept has proven to be severely limited in its ability to provide stable and accurate feed rate control. The V-RAD invention provides a new and unique method of feed rate control designed to replace the variable area orifice concept and to provide a stable and accurate method of feed rate control.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R<N redundant elements in dependence on a K-bit input address which is applied to a 1-out-of-N decoder, and which addresses the regular elements. For each redundant element, a bypass circuit is provided and has in each case a reference bit transmitter for supplying K reference bits that are programmable by selective destruction or by selective introduction of conductive links in order to set a comparison device to the identification of a selected address. If the relevant address is identified, the bypass circuit addresses the redundant element assigned to it while switching off the 1-out-of-N decoder, provided that it is sensitized. For its sensitization, each bi-stable-circuit checks M<K preselected specimens of the reference bits in order to set the relevant bypass circuit into an active state if the binary values of these reference bits differ from a chosen bit combination.

Abstract: A semiconductor memory apparatus includes a first and second memory bank. Each of these memory banks has a plurality of row and column lines and at least one redundant column line. An activation device selectively activates the redundant column line, thereby causing the redundant column line to become a replacement line for a defective column line. The activation device includes a plurality of programmable addressing fuses, and a programmable selection fuse having at least two electrical selection fuse states. The programmable selection fuse is configured such that an addressing fuse in the first selection fuse state is electrically associated with the first memory bank and an addressing fuse in the second selection fuse state is electrically associated with the second memory bank.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R<N redundant elements in dependence on a K-bit input address which is applied to a 1-out-of-N decoder, and which addresses the regular elements. For each redundant element, a bypass circuit is provided and has in each case a reference bit transmitter for supplying K reference bits that are programmable by selective destruction or by selective introduction of conductive links in order to set a comparison device to the identification of a selected address. If the relevant address is identified, the bypass circuit addresses the redundant element assigned to it while switching off the 1-out-of-N decoder, provided that it is sensitized. For its sensitization, each bi-stable-circuit checks M<K preselected specimens of the reference bits in order to set the relevant bypass circuit into an active state if the binary values of these reference bits differ from a chosen bit combination.

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.