Abstract: The fractional division frequency synthesizer comprises a digital ramp generator producing a digital correction ramp controlled by a frequency control programmer; a divide by N divider coupled to an output of a voltage controlled oscillator with the divider being controlled by the program, where N is a selected one of an integer and a fraction one or greater; a digital phase detector coupled to a reference clock and the output of the divider to provide a digital phase error signal; a digital adder coupled to an output of the ramp generator and the phase detector to produce a ramp corrected digital phase error signal; and circuit arrangement coupled to an output of the adder and a control input of the controlled oscillator to convert the ramp corrected digital phase error signal to a ramp corrected analog phase error signal to control the controlled oscillator and thereby provide a controlled frequency signal at the output thereof.

Abstract: The digital sample and hold phase detector to compare the phase relationship between input pulses and a high frequency reference clock comprises a digital counter arrangement coupled to count the high frequency reference clock to produce a digital ramp signal and a digital sampling arrangement coupled to at least the input pulses and an output of the counter arrangement to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

Abstract: A phase locked loop employed in a synthesizer includes a coarse tuning means to enable the VCO in the loop to be tuned within the acquisition range of the loop to thus enable the loop to fine tune the VCO to the desired output frequency. The coarse tuning means is removed from the loop when the VCO frequency is within the acquisition range.

Abstract: A phase detector for a phase locked loop (PLL) to be employed in a wideband synthesizer generates a ramp waveform at an output. The ramp waveform has a positive slope during the reference signal; when a sample pulse is received by the circuitry, the slope of the ramp is changed to a negative slope. Hence, the output of the detector will be negative or positive depending upon the difference in phase between the reference and sample frequencies. The ramp voltage is sampled and held by a suitable circuit which provides an error signal for controlling a VCO.