Abstract: An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle ?. The coarse stage rotation includes a memory device storing pre-computed cosine ?M and sine ?M values for fast retrieval, where ?M is a radian angle that corresponds to a most significant word (MSW) of the input angle ?. The fine stage rotation uses one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. The rotator consolidates operations into a small number of reduced-size multipliers, enabling efficient multiplier implementations such as Booth encoding, yielding a smaller and faster overall circuit.

Abstract: A rectangular-to-polar-converter receives a complex input signal (having X0 and Y0 components) and determines an angle ? that represents the position of the complex signal in the complex plane. The rectangular-to polar-converter determines a coarse angle ?1 and a fine angle ?2, where ?=?1+?2. The coarse angle ?1 is obtained using a small arctangent table and a reciprocal table. These tables provide just enough precision such that the remaining fine angle ?2 is small enough to approximately equal its tangent value. Therefore the fine angle ?2 can be obtained without a look-up table, and the fine angle computations are consolidated into a few small multipliers, given a precision requirement. Applications of the rectangular-to-polar converter include symbol and carrier synchronization, including symbol synchronization for bursty transmissions of packet data systems. Other applications include any application requiring the rectangular-to-polar conversion of a complex input signal.

Abstract: A trigonometric interpolator interpolates between two data samples at an offset &mgr;, where the two data samples are part of a set of N data samples. The trigonometric interpolator fits a trigonometric polynomial to the N data samples and evaluates the trigonometric polynomial at the offset &mgr;. The trigonometric inteprolator can be utilized for data rate changing and to correct mismatches between received samples and transmitted symbols. Simulations demonstrate that the trigonometric interpolater attains better performance than “conventional” interpolators, while simultaneously reducing the required hardware. In embodiments, the filter response of the trigonometric interpolator can be modified to achieve an arbitrary frequency response in order to enhance the interpolator performance. More specifically, the frequency response of the interpolator can be shaped to effectively correspond with the frequency response of the input data samples and the offset &mgr;.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . .

Abstract: A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities.