Patents by Inventor Alan Nakamoto

Alan Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10735004
    Abstract: An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 4, 2020
    Assignee: Microchip Technology Inc.
    Inventors: Matthew Kian Chin Yap, Alan Nakamoto
  • Patent number: 6185713
    Abstract: A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: February 6, 2001
    Assignee: PMC-Sierra Ltd.
    Inventors: Alan Nakamoto, Kris Iniewski, Monika Swic, Curtis Lapadat, Larrie Simon Carr