Abstract: An electrical component is provided by metallizing holes that extend through a glass substrate. The electrical component can be fabricated by forcing a suspension of electrically conductive particles suspended in a liquid medium through the holes. The suspension can be forced into the holes under an air pressure differential such as a vacuum force, a centrifugal force, or an electrostatic force. The liquid medium in the holes can be dried, and the particles can be sintered. The particles can further be packed in the hole. Alternatively or additionally, the particles can be pressed against the outer surfaces of the substrate to produce buttons.

Abstract: In semiconductor processing, the critical dimensions of structures formed on a wafer are controlled by first developing photoresist on top of a film layer on a wafer using a developer tool, the photoresist development being a function of developer tool process variables including temperature and length of time of development. After developing the photoresist, one or more etching steps are performed on the film layer on the wafer using an etch tool. After the one or more etching steps are performed, critical dimensions of structures at a plurality of locations on the wafer are measured using an optical metrology tool. After the critical dimensions are measured, one or more of the developer tool process variables are adjusted based on the critical dimensions of structures measured at the plurality of locations on the wafer.

Abstract: The profile of a structure having a region with a spatially varying property is modeled using an optical metrology model. A set of profile parameters is defined for the optical metrology model to characterize the profile of the structure. A set of layers is defined for a portion the optical metrology model that corresponds to the region of the structure with the spatially varying property, each layer having a defined height and width. For each layer, a mathematic function that varies across at least a portion of the width of the layer is defined to characterize the spatially varying property within a corresponding layer in the region of the structure.

Abstract: A polishing pad includes a plurality of polishing surfaces, a first group of the polishing surfaces made of a first material having a first coefficient of friction and a second group of the polishing surfaces made of a second material having a second coefficient of friction. The first and second groups of polishing surfaces may be arranged over the polishing pad so as to provide a non-planar material removal profile. The polishing surface layout may be designed by evaluating a material removal profile for an existing polishing pad of known characteristics, observing how variations in polishing surface densities and/or coefficients of friction affect that material removal profile, and then mapping the polishing surface coefficients of friction and density profiles to the subject polishing pad layout.

Abstract: A patterned structure in a wafer is created using one or more fabrication treatment processes. The patterned structure has a treated and an untreated portion. One or more diffraction sensitivity enhancement techniques are applied to the structure, the one or more diffraction sensitivity enhancement techniques adjusting one or more properties of the patterned structure to enhance diffraction contrast between the treated portion and untreated portions. A first diffraction signal is measured off an unpatterned structure on the wafer using an optical metrology device. A second diffraction signal is measured off the patterned structure on the wafer using the optical metrology device. One or more diffraction sensitivity enhancement techniques are selected based on comparisons of the first and second diffraction signals.

Abstract: A patterned structure in a wafer is created using one or more fabrication treatment processes. The patterned structure has a treated and an untreated portion. One or more diffraction sensitivity enhancement techniques are applied to the structure, the one or more diffraction sensitivity enhancement techniques adjusting one or more properties of the patterned structure to enhance diffraction contrast between the treated portion and untreated portions. A first diffraction signal is measured off an unpatterned structure on the wafer using an optical metrology device. A second diffraction signal is measured off the patterned structure on the wafer using the optical metrology device. One or more diffraction sensitivity enhancement techniques are selected based on comparisons of the first and second diffraction signals.

Abstract: The profile of a structure having a region with a spatially varying property is modeled using an optical metrology model. A set of profile parameters is defined for the optical metrology model to characterize the profile of the structure. A set of layers is defined for a portion the optical metrology model that corresponds to the region of the structure with the spatially varying property, each layer having a defined height and width. For each layer, a mathematic function that varies across at least a portion of the width of the layer is defined to characterize the spatially varying property within a corresponding layer in the region of the structure.

Abstract: In semiconductor processing, the critical dimensions of structures formed on a wafer are controlled by first developing photoresist on top of a film layer on a wafer using a developer tool, the photoresist development being a function of developer tool process variables including temperature and length of time of development. After developing the photoresist, one or more etching steps are performed on the film layer on the wafer using an etch tool. After the one or more etching steps are performed, critical dimensions of structures at a plurality of locations on the wafer are measured using an optical metrology tool. After the critical dimensions are measured, one or more of the developer tool process variables are adjusted based on the critical dimensions of structures measured at the plurality of locations on the wafer.