Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Abstract: A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.

Abstract: A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable.