Patents by Inventor Alan Paussa

Alan Paussa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137033
    Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Marc Kanzian, Alan Paussa, Francesco Conzatti, Joseph Semmler
  • Patent number: 10790842
    Abstract: A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 29, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alan Paussa, Francesco Conzatti
  • Patent number: 10651869
    Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 12, 2020
    Assignees: Intel IP Corporation, Intel Corporation
    Inventors: Davide Ponton, Michael Kalcher, Alan Paussa, Edwin Thaller, Franz Kuttner, Daniel Gruber