Abstract: A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate or base of the transistor which is providing the particular logic state. This control is responsive to the magnitude of the power supply voltage. An impedance which varies in resistance with supply voltage is placed in series between the positive power supply terminal and the gate or base of the output transistors.

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the ends of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors in controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt.

Abstract: A four-IGFET memory cell is utilized as a static (or DC) memory cell rather than as a dynamic memory cell. When the memory cell is in the standby mode an intermediate voltage is applied to a selection conductor coupled to the gates of the gating IGFETS of the memory cell. The intermediate voltage applied to the "X" selection conductor under standby conditions is slightly in excess of two IGFET threshold voltages, and is sufficient to maintain the stored logical state, yet causes very little power to be dissipated by the memory cell. A full logical "1" level is applied to the selection conductor during either a read operation or a write operation if the memory cell is selected, i.e. is addressed by the decoding circuitry in response to chip select and address inputs of a memory chip incorporating the memory cell. If the memory cell is unselected during a read or write operation, a logical "0" is applied to the selection conductor.