Abstract: An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the column decoding function. This prevents the bit sense column selection conductor from being affected when an internal column selection clock signal is generated. This results in a substantial savings in power dissipation which would be required if it were necessary to provide circuitry to disable the internal column selection clock generator circuit during an unselected memory cycle.

Abstract: An output circuit including a latch circuit and a push-pull output driver driven by the latch circuit is controlled by disable circuit which disables the output circuit when a random access memory semiconductor chip on which the output circuit is located undergoes an unselected memory cycle, i.e., is unselected. The disable circuit includes a bootstrap NOR gate having a series power switching IGFET coupling its load device to a voltage supply conductor. The power switching IGFET is controlled by the output of the disable circuit so that the disable circuit shuts off its own power at the same time it disables the output latch when the random access memory chip undergoes an unselected memory cycle. Essentially, the disable circuit operates in such a manner that it shuts off its own power and also disables the output circuit in response to a second input signal, conditioned on the occurrence of an earlier first signal.

Abstract: A decoder for a semiconductor MOS random access memory includes a dynamic NOR gate having a first output. The decoder also includes a selection MOSFET for providing a selection signal to a selection conductor connected to a row or column of an array of storage cells of said random access memory. The gate electrode of the selection MOSFET is connected to the output node of the NOR gate. The drain of the selection MOSFET is connected to a signal conductor adapted to having a signal applied thereto which is a function of a read/write signal applied to said random access memory. The source of the selection MOSFET is connected to the selection conductor. A feedback MOSFET is coupled between the output of the dynamic NOR gate and the selection conductor and has its gate electrode controlled by the signal which is a function of the read/write input signal. When the NOR gate is selected by a particular combination of address input variables, its initially precharged output node is discharged to ground.

Abstract: A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and a storage node of one of the dummy storage cells of each row of storage cells. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected. Charge initially stored in the selected storage cell is redistributed on the opposite sense-write conductor and is subsequently amplified by the sense amplifier, and produced in inverted amplified form at the storage node of the dummy storage cell.