Abstract: Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.

Abstract: A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A system for testing a device under test (DUT) can include: a test controller unit that includes a first memory is operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern can be selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit can interface with the DUT for testing. Portions of the data pattern can be selectively transferred from the second memory to the third memory for application to the DUT.

Abstract: A method for evaluating test results for a memory module. Contents of a data stream are reviewed for one or more sections of the memory module. A plurality of counters is incremented when a defective portion is encountered in the data stream for a first section of the memory module. Values of the plurality of counters are compared to corresponding threshold values. Provided two or more counter values are at or above their threshold values, the first section is marked as bad, all defective portions of the first section are removed from the test data stream, and a failure header indicating that the first section is bad is stored and because of which counters in an error cache, otherwise each defective portion of the first section is marked as good in the data stream provided an error correction counter value of the plurality of counter values is equal to or below a first threshold value.

Abstract: A method according to one embodiment of the present invention for evaluating test results for a memory module. The method comprises reviewing contents of a test data stream for one or more sections of the memory module. A first counter is incremented when a defective portion is encountered in the test data stream for a first section of the one or more sections of the memory module. Each defective portion of the first section is marked as good in the test data stream so long as a first counter value is equal to or below a first threshold value. Data from the test data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the first counter passes a first threshold value.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a “must-repair” row or column, and otherwise how many errors the corresponding row or column contain.

Abstract: Input to a device under test (DUT) is reconstructed. For each trigger cycle of a tester in which data is to be input to the DUT stimulus, data is prepared to be placed as stimulus on pins of the DUT. Response information obtained from the DUT during a previous trigger cycle is used to construct formatting information used to adjust a value of the stimulus data. Reconstruction information sufficient to reconstruct the stimulus data is stored. The reconstruction information includes the formatting information. The reconstruction information is used to reconstruct the stimulus data placed on the pins of the device under test.

Abstract: The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT.

Abstract: A method and apparatus permits use of a tester memory (31) as storage for an inversion mask. The inversion mask indicates to the tester which cells in a DUT memory (14) are logically inverted during testing. Data information and the inverse of the data information is input into a first data multiplexer (802). The stored inversion mask (902–908) is used to independently select a data information bit or its inverse for presentation as a masked output (814) at the output of the first data multiplexer (802).

Abstract: An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction is a binary word specifying a branch condition address and a conditional instruction. The branch unit has a programmable flag selection memory and a plurality of first flag selectors and determines in hardware whether to branch according to the conditional instruction. Each first flag selector accepts a plurality of available flags and selects a flag based upon contents in the flag selection memory. A second flag selector accepts the flags from the first flag selectors and selects one of the flags to present as a branch flag based upon the branch condition address. The branch flag indicates whether to branch to the destination address.

Abstract: Waveforms of input/output signals for a device under test (DUT) are simultaneously displayed. A user is presented with an interface that allows the user to specify different modes for capturing data for different input/output signals for the DUT. Data for the different input/output signals are captured in accordance with different data capture mechanisms dependent upon the different modes specified by the user. Based on the data, waveforms for each of the different input/output signals are simultaneously displayed.

Abstract: A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger.

Abstract: A waveform for an input/output signal for a device under test (DUT) is displayed. Data for the input/output signal is captured in accordance with a first data capturing mechanism. The waveform for the input/output signal is displayed using the captured data. A user is provided with an interface that allows the user to select a portion of the waveform for recapture using a second data capturing mechanism. Data for a portion of the input/output signal, corresponding to the portion of the waveform selected for recapture, is recaptured. The recapturing of data is performed using the second data capturing mechanism. The waveform for the input/output signal is redisplayed. The data recaptured using the second data capturing mechanism is used for displaying the portion of the waveform selected for recapture. The data captured in accordance with the first data capturing mechanism is used for displaying remaining portions of the waveform not selected for recapture.

Abstract: A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs.

Abstract: A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.