Abstract: A dual rail power supply system and a method for providing a first voltage and a second voltage to a load are presented. The power supply system draws a load current from the dual rail power supply system. The system has a first voltage rail for coupling to a first terminal of the load, a second voltage rail for coupling to a second terminal of the load, a first power converter to provide the first voltage at the first voltage rail, a second power converter to provide the second voltage at the second voltage rail, a third power converter comprising a first output coupled to the first voltage rail and a second output coupled to the second voltage rail. The third power converter generates a slave current and provides the slave current to the load such that the load current comprises the slave current, during a first mode.

Abstract: A power management circuit is provided with groups of switches and a single shared inductor and is selectively configured in a first mode to act as a buck regulator and a second mode to act as a buck-boost regulator. There is a two-stage circuit topology, where both charging and regular operation of the device can be optimized. There is a switching charger integrated circuit that can be dedicated to performing a charging function, and there is a DC-DC power management integrated circuit that can be dedicated to regulating the system voltage provided by the battery while the battery is discharging.

Abstract: A method and circuit that allows a charger port to source a slow charging voltage and current for one type of portable device and an adjustable voltage and current for a second type of portable device. The second type of portable device communicates with the charger port to establish a voltage and current that the portable device is capable of accepting. The portable device communicates with a charger port by load modulation structured for establishing a communications protocol for communicating a voltage and current level acceptable to the portable device.

Abstract: A power management circuit is provided with groups of switches and a single shared inductor and is selectively configured in a first mode to act as a buck regulator and a second mode to act as a buck-boost regulator. There is a two-stage circuit topology, where both charging and regular operation of the device can be optimised. There is a switching charger integrated circuit that can be dedicated to performing a charging function, and there is a DC-DC power management integrated circuit that can be dedicated to regulating the system voltage provided by the battery while the battery is discharging.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage block for storing the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel pre-charge mechanism for pre-charging the pixel elements employing a back to back pre-charge operation applied to a row and/or column drive activated pixel element display operation. The back to back pre-charge operation signifies that during every other operating sequence a pre-charge operation is replaced by an activated pixel element display operation.

Abstract: An anode driver chip and a cathode driver chip attached to an OLED device by means of anisotropic glue. The fine structure of the attachment means requires inspection to determine any resulting open and short conditions. The anode driver circuits comprise an output current detection that allows open circuit testing of the contact between the OLED device and the anode driver chip. The cathode driver circuits comprise a voltage detection circuit that allows both open and short circuit detection between cathode driver pads.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage and processing block for the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel display operation for displaying pixel elements employing an advanced multi line addressing operation applied to a row and/or column drive activated pixel element display operation.

Abstract: A circuit for a flat panel display includes an image data storage and processing block, a display and timing controller block, an image pixel matrix containing a multitude of row and column arranged pixel elements, one or more controlled row and column driver blocks, and a tagged multi line addressing (TMLA) pixel element display operation. That TMLA operation comprises a decomposition of image data by searching all lines of an image for groups of identical lines by tagging each of these lines with a unique code and thus decomposes image data into multi line and single line domain data in such a way, that lines with matching tags, indicating their common and identical contents, are outputted as image data into related groups of the multi line domain with no left over residual image data and thus the related groups in the single line domain data are all zeroes.

Abstract: Methods for PWM precharging of organic light emitting diodes (OLEDs) have been disclosed. Image quality has been improved by including the light generated during pre-charge phase is included in the overall budget. The approach invented is especially beneficial to displays using Multi-Line Algorithms (MLA). Constant discharge time for anodes, discharging the anodes to just below the luminance level saves power by reducing the pre-charge requirements for the next driving phase. High impedance terminal (HiZ) discharge is performed after a fixed discharge of anodes.

Abstract: A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage block for storing the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel pre-charge mechanism for pre-charging the pixel elements employing a back to back pre-charge operation applied to a row and/or column drive activated pixel element display operation. The back to back pre-charge operation signifies that during every other operating sequence a pre-charge operation is replaced by an activated pixel element display operation.

Abstract: A circuit for a flat panel display includes an image storage block, a display and timing controller block, an image pixel matrix containing a multitude of row and column arranged pixel elements, also one or more controlled row and column driver blocks, and a pixel display operation employing the extended multi line addressing (XMLA) operation. That XMLA operation comprises a decomposition of image data by analyzing image data from at least two lines from the image data but employing as many lines of the image data as possible according to a certain ‘best match’ criterion directly expanding these operations over their ‘widest possible range’ of lines using that ‘best match’ criterion to find within multiple lines common parts of contents, then separating these common parts into a multi line and the residual parts into a single line data domain thus allowing for a separate display of those data domains.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage and processing block for the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel display operation for displaying pixel elements employing an advanced multi line addressing operation applied to a row and/or column drive activated pixel element display operation.

Abstract: A circuit for a flat panel display includes an image data storage and processing block, a display and timing controller block, an image pixel matrix containing a multitude of row and column arranged pixel elements, one or more controlled row and column driver blocks, and a tagged multi line addressing (TMLA) pixel element display operation. That TMLA operation comprises a decomposition of image data by searching all lines of an image for groups of identical lines by tagging each of these lines with a unique code and thus decomposes image data into multi line and single line domain data in such a way, that lines with matching tags, indicating their common and identical contents, are outputted as image data into related groups of the multi line domain with no left over residual image data and thus the related groups in the single line domain data are all zeroes.

Abstract: A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.

Abstract: A DC-to-DC voltage converter having an active charge/discharge circuit enabling the definition of any output voltage within its operating range has been achieved. A comparator compares the output voltage of a voltage converter with a defined reference voltage. This reference voltage can be easily modified within its operating range. In case the output voltage of the voltage converter is higher than said reference voltage a “reservoir” capacitor at the output of said voltage is discharged via an active charge/discharge circuit until the output voltage equals said reference voltage. Said active charge/discharge circuit is activated via a latch by said comparator. The invention is applicable for any type of DC-to-DC converters, such as e.g. charge pumps, buck converters and boost converters.

Abstract: Circuits and methods to shut down any charge pump having any number of stages have been achieved. The invention is especially relevant to charge pumps, which have a supply that is incapable of sinking significant current, such as a supply derived from an LDO. The shutdown can be done either until all stages have zero voltage or until all stages have the input voltage level. The shutdown is performed in a staged manner, from the output backwards to the input, so there is reduced charge sharing between the capacitors so that no voltage exceeds its normal operating range. An additional advantage of the present invention is that the charge pump can be switched back on, before the shutdown sequence is complete, with all internal and external nodes of the charge pump staying within their normal operating range.

Abstract: Circuits and methods to shut down any charge pump having any number of stages have been achieved. The invention is especially relevant to charge pumps, which have a supply that is incapable of sinking significant current, such as a supply derived from an LDO. The shutdown can be done either until all stages have zero voltage or until all stages have the input voltage level. The shutdown is performed in a staged manner, from the output backwards to the input, so there is reduced charge sharing between the capacitors so that no voltage exceeds its normal operating range. An additional advantage of the present invention is that the charge pump can be switched back on, before the shutdown sequence is complete, with all internal and external nodes of the charge pump staying within their normal operating range.

Abstract: A DC-to-DC voltage converter having an active charge/discharge circuit enabling the definition of any output voltage within its operating range has been achieved. A comparator compares the output voltage of a voltage converter with a defined reference voltage. This reference voltage can be easily modified within its operating range. In case the output voltage of the voltage converter is higher than said reference voltage a “reservoir” capacitor at the output of said voltage is discharged via an active charge/discharge circuit until the output voltage equals said reference voltage. Said active charge/discharge circuit is activated via a latch by said comparator. The invention is applicable for any type of DC-to-DC converters, such as e.g. charge pumps, buck converters and boost converters.