Abstract: A method of communicating from a transmitter to a receiver over a communication medium. For the transmitter, the method includes the step of formatting data into a data stream to be communicated across the communications medium. This data stream comprises a plurality of headers (PACK HEADER). Moreover, for each of the plurality of headers, the method performs two steps. First, the method modifies information encoded by the header by performing a bitwise logical operation between selected bits of the header (B) with a predetermined bit pattern (A). Second, the method transmits the plurality of headers on to the communications medium. For the receiver, the method includes the step of receiving the plurality of headers from the communications medium. Additionally, for each of the received headers, the receiver recovers the information encoded by the header.

Abstract: A method of communicating from a transmitter to a receiver over a communications medium. For the transmitter, the method includes the step of formatting data into a data stream to be communicated across the communications medium. This data stream comprises a plurality of headers (PACK HEADER). Moreover, for each of the plurality of headers, the method performs two steps. First, the method modifies information encoded by the header by performing a bitwise logical operation between selected bits of the header (B) with a predetermined bit pattern (A). Second, the method transmits the plurality of headers on to the communications medium. For the receiver, the method includes the step of receiving the plurality of headers from the communications medium. Additionally, for each of the received headers, the receiver recovers the information encoded by the header.

Abstract: A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V.sub.m. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V.sub.m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.

Abstract: The disclosure relates to integrated circuit resistors and matched resistor pairs wherein each resistor is split into plural segments, each segment having a separate field plate thereover, each segment having the field plate associated therewith connected to the non-common node thereof. In the case of the matched resistor pair, the interconnections between the segment of each resistor overlap. The segments are preferably substantially rectangular in shape with the major axes of all segments parallel to each other.