Abstract: There is described an optical modulation system for transmitting modulated optical light. The system comprises an electro-optic modulator having at least two arms through which light is transmitted and an imbalance electrode located on at least one arm. A current source is configured to inject current into the imbalance electrode for modifying the phase of light passing through the arm. A dither generator is configured to modulate the injected current, or bias voltage applied to at least one of the arms, with a dither signal. A phase sensitive detector is configured to detect an error in the phase of light emitted by the modulator. An operating point controller is configured to monitor the detected phase error and adjust the current injected into the imbalance arm so as to compensate for the detected error and thereby control an operating point of the modulator.

Abstract: There is described an optical modulation system for transmitting modulated optical light. The system comprises an electro-optic modulator having at least two arms through which light is transmitted and an imbalance electrode located on at least one arm. A current source is configured to inject current into the imbalance electrode for modifying the phase of light passing through the arm. A dither generator is configured to modulate the injected current, or bias voltage applied to at least one of the arms, with a dither signal. A phase sensitive detector is configured to detect an error in the phase of light emitted by the modulator. An operating point controller is configured to monitor the detected phase error and adjust the current injected into the imbalance arm so as to compensate for the detected error and thereby control an operating point of the modulator.

Abstract: An automatic bias controller for an optical modulator is provided. The automatic bias controller comprises a driver for providing an electrical data signal to the modulator and a bias voltage source for providing a bias voltage to the modulator. A microprocessor provides a low frequency digital modulation signal, which is converted to an analogue modulation signal by a digital to analogue converter. The analogue modulation signal is applied to the bias voltage source (so as to modulate the bias voltage) or to the driver (so as to modulate the amplitude of the data signal). Intensity detectors for detecting the intensity of light emitted by the modulator are provided, and an analogue to digital converter converts the output of the intensity detectors to a digital intensity signal which is passed to the microprocessor. The digital intensity signal is analysed, and the bias voltage source instructed to adjust the bias voltage on the basis of the analysed signal.

Abstract: An automatic bias controller for an optical modulator is provided. The automatic bias controller comprises a driver for providing an electrical data signal to the modulator and bias means for providing a bias voltage to the modulator. A microprocessor provides a low frequency digital modulation signal, which is converted to an analogue modulation signal by a digital to analogue converter. The analogue modulation signal is applied to the bias means (so as to modulate the bias voltage) or to the driver (so as to modulate the amplitude of the data signal). Intensity detection means for detecting the intensity of light emitted by the modulator are provided, and an analogue to digital converter converts the output of the intensity detection means to a digital intensity signal which is passed to the microprocessor. The digital intensity signal is analysed, and the bias means instructed to adjust the bias voltage on the basis of the analysed signal.

Abstract: A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131), connected in cascade, means for applying digital data signals to the first latch, means for clocking (701) the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means (210) to which are applied the digital data signals (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X=B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch.