Patents by Inventor Alan Varner

Alan Varner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210175149
    Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Inventors: Kirby Gaulin, Emily Lautoa, Alan Varner
  • Patent number: 10957618
    Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Apex Microtechnology, Inc.
    Inventors: Kirby Gaulin, Emily Sataua, Alan Varner
  • Publication number: 20190371696
    Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Inventors: Kirby Gaulin, Emily Sataua, Alan Varner
  • Publication number: 20050012552
    Abstract: Systems and methods to improve bias matching (e.g., for a current feedback amplifier) are described. A compensation signal is combined with one or more bias signals to mitigate mismatch between the bias signals. The compensation signal is generated to correspond to the mismatch between the bias signals. This approach can be implemented to improve performance of an associated amplifier, such as by reducing offset at an input of a portion of the amplifier (e.g., an input buffer) that is biased by the bias signals.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 20, 2005
    Inventors: Alan Varner, Paul Damitio