Abstract: A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

Abstract: A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Abstract: A method and implementing system are provided in which specific byte requests made by a functional unit within a computer system effect the return of a word containing the requested byte to a register device within a CPU. The returned word is stored "as is" and without alignment, together with mask and alignment data indicative of the location of the requested byte within the stored word. Alignment relative to the requested byte is thereafter accomplished using the mask and alignment data just before use of the requested byte by the functional unit. The alignment function is thereby accomplished outside of the processor critical path which obviates the typical memory-processor mismatch delay inherent in prior art data alignment networks and substantially shortens the critical path in the memory access stage of the processor's pipeline.