Abstract: In certain embodiments, a system is provided for image capture that includes a unit cell that includes a Capacitor TransImpedance Amplifier (CTIA) subcircuit, a Source Follower per Detector (SFD) subcircuit, and a Direct Injection (DI) subcircuit. The unit cell may operate using one of the subcircuits selected in response to a control signal. A column amplifier may be coupled to the unit cell. The column amplifier may be operable to receive an intermediate signal from the unit cell and couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal. The column amplifier may generate an output signal from the intermediate signal using the coupled components of the column amplifier.

Abstract: In certain embodiments, a system is provided for image capture that includes a unit cell that includes a Capacitor TransImpedance Amplifier (CTIA) subcircuit, a Source Follower per Detector (SFD) subcircuit, and a Direct Injection (DI) subcircuit. The unit cell may operate using one of the subcircuits selected in response to a control signal. A column amplifier may be coupled to the unit cell. The column amplifier may be operable to receive an intermediate signal from the unit cell and couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal. The column amplifier may generate an output signal from the intermediate signal using the coupled components of the column amplifier.

Abstract: A dual band imager includes a radiation absorbing layer for absorbing light of a first wavelength coupled to a readout circuit (ROIC), and at least one radiation detector for detecting light of a second wavelength coupled to the ROIC via a corresponding opening extending through the radiation absorbing layer.

Abstract: Disclosed is a High Dynamic Range Dual Mode (HDR-DM) input circuit unit cell (10) for use with an infrared (IR) radiation detector (D1). The readout circuit unit cell includes a plurality of transistors (M1, M2, M3 and M4), switches (S1, S2 and S3), and capacitances (Cfb, Cbl and CSH) that are controllably coupled together to form, in a first mode of operation below an illumination level threshold, a CTIA input circuit (12), and to form, in a second mode of operation above the illumination level threshold, a lower gain SFD input circuit (14).

Abstract: A readout circuit (1) has an x-row by y-column array of readout unit cells (10) each having an input for coupling to an output of a radiation detector (16) and an output that is switchably coupled to one of y column output lines (21). Each unit cell includes a driver transistor (12) having a gate terminal coupled to the detector, a source terminal coupled to a source voltage, and a drain terminal switchably coupled to a drain voltage through one of y loads, such as one of y current sources (18). The drain terminal is switchably coupled to the one of y current sources through an output multiplexer switch (20). The current source is a common current source for all of the x unit cells coupled to a same one of the y column output lines. The unit cell further includes a capacitance coupled between the gate and drain terminals, and a reset switch also coupled between the gate and drain terminals.

Abstract: A current mirror circuit 10 is coupled to a first and a second photodetector 18 and 20 and differentially couples together the two photodetectors to an amplifier 12 such that a resulting differential output current is independent of the intrinsic responsivity difference between the two photodetectors. The circuit includes a first transistor 14 having an input terminal coupled to an output terminal of the first photodetector and a second transistor 16 having an input terminal coupled to an output terminal of the second photodetector. A capacitance 22 is coupled between a control terminal of the first transistor and a control terminal of the second transistor, the control terminal of the first transistor further being coupled to the input terminal of the first transistor. A first switch 24 is coupled between the control terminal of the second transistor and the input terminal of the second transistor.