Abstract: A high T.sub.c oxide superconductive switching device [10] formed on a substantially planar substrate [18] includes a base electrode [12] comprised of a layer or film of anisotropic superconducting material. The layer has a first crystalline axis [c] along which a magnitude of an energy gap of the material is less than an energy gap of the material along other crystalline axes. The superconductive switching device further includes at least one injector electrode [14] forming a planar [16] or an edge tunneling junction with the base electrode for injecting, under the influence of a bias potential eV, quasiparticles into the base electrode. The first crystalline axis is aligned in a predetermined manner with the tunneling junction for optimizing a quasiparticle injection efficiency of the tunneling junction.

Abstract: A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.

Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.

Abstract: A low band gap semiconductor heterostructure having a surface adaptable to planar processing and all semiconductor properties supported by a fabrication constraint relaxing substrate that does not provide a low impedance parallel current path. A superconductor normal superconductor device of n-InAs-100 nanometers thick with niobium superconductor electrodes spaced 250 nanometers apart and a 100 nanometer gate in the space. The N-InAs is supported by an undoped GaAs layer on a semi-insulating GaAs substrate. A heterojunction field effect transistor device having a GaAlAs gate over a channel 100 nanometers thick on an undoped GaAs layer on a semi-insulating GaAs substrate.

Abstract: Combining an evaporation source and an ion beam source to provide a crucible anode surface, and heating that crucible anode surface to a high enough temperature to cause evaporation of anode material, provides for emission of atoms and ions selectively and independently controllable and directed along the identical path. A high melting point material auxiliary anode, connected to the crucible anode by a variable resistance, provides independent control of the vapor flux by selectively shifting the discharge current from auxiliary anode to crucible anode.The crucible anode contains the material which is to be evaporated. A gas plasma discharge is supplied between a heated cathode filament and the heated crucible anode. Electrons carrying a discharge current bombard the crucible anode material surface, causing a temperature rise which causes an increase in discharge current.