Abstract: A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known as tie nets, are not timing critical signals that, when poorly implemented can get in the way of functional signals in an integrated circuit. The current method is to connect the pin to the nearest power connections of the correct polarity. This requires some amount of wiring resources that may be needed for other functions or pin access. Accordingly, the present invention avoids this situation by avoiding wiring.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: A small bore tubing system employs affordance to assist distinction between different applications of medical tubing and their interconnections, as well as unique keying to avoid misconnection between tubing of different applications. Said affordance is by shape of a grip on connectors of the system, which shapes provide both visual and tactile application-specific affordance (eg. spine and ribs to indicate neuraxial application). Further mechanism affordance ensures appropriate connection mechanism is employed. A kit of components of a medical small-bore tubing connection system has a first converter (14), a second converter (30), a syringe (10) and a needle (50). Each converter (14, 30) has a through bore, a standard female (16) and male (36) connector, and a “different” male (18) and female (32) connector element. The first converter (14) has a latching mechanism (control ring) (20) on the different male connector (18) and which is adapted to engage a flange (34) of the corresponding female connector.

Abstract: A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation.