Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than the prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met.

Abstract: Non-volatile memory systems utilizing storage address tables are disclosed. A non-volatile memory system may include a non-volatile memory, a memory die command manager in communication with the memory, and a command manager in communication with the memory die command manager. The memory die command manager is configured to identify a free die of the memory to store data, where the free die of the memory is identified independent of a host logical block address associated with the data; store the data at a physical block address at the free die; and generate an entry in a first address table, the first address table associating the physical block address with a virtual logical block address. The command manager is configured to generate an entry in a second address table, the second address table associating the virtual logical block address with a host logical block address received with the host write command.

Abstract: Ring bus architectures for use in a memory module are disclosed. A memory module may include a ring bus controller and a bus bridge positioned on a primary ring bus. The memory module also includes a secondary ring bus in communication with the bus bridge and a plurality of non-volatile memory units. The ring bus controller is configured to send a configuration command to the bus bridge via the primary bus ring, where the configuration command includes an indication to route future commands and/or data to the secondary ring bus extending from the bus bridge. The bus bridge is configuration to, in response to the configuration command, configure the bus bridge to route future commands and/or data from the primary ring bus to the secondary ring bus.

Abstract: A non-volatile memory system may have a group of non-volatile memory cells having a plurality of predetermined portions, where each predetermined portion is associated with an open host write block of a different host data type than each other predetermined portion. A host data router directs received data from a host to an appropriate predetermined portion based on a determined data type. A maintenance data router, based on predetermined minimum capacity overprovisioning targets for each predetermined portion, operates to adjust an amount of overprovisioning of physical capacity among the plurality of predetermined portions to reduce write amplification and increase performance in predetermined portions having data with a higher probability of host update. The method may include selecting a particular predetermined portion and a particular block within the selected predetermined portion on which to perform a maintenance operation to achieve the desired capacity overprovisioning.

Abstract: Systems and methods for implementing adaptive memory layers in a storage system are disclosed. A storage system may include a non-volatile memory with memory cells configurable to each of a plurality of bit-per-cell capacities and divided into dynamically re-sizable memory layers defined by memory cells of a particular capacity. A memory layer adjustment module associated with a controller of the storage system is configured to, upon detection of a maintenance trigger, compare the amount of valid data and overprovisioning in each layer to a target amount and to redistribute valid data and physical capacity among the memory layers according to a predetermined table or algorithm in order to optimize performance of each memory layer.

Abstract: A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer.

Abstract: A system and method for managing program cycles in a multi-layer memory are disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request. The programming cycle may be a set of a host data write programming operation and any maintenance programming operations on an amount of data already programmed in the plurality of memory layers that is necessary to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the host request, and the amount of data to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle.

Abstract: A flash memory system having unequal number of memory die and method for operation are disclosed. The memory system includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die and associated different physical capacity per control line.

Abstract: A hybrid non-volatile system uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit their relative advantages. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the memory or read back to the host.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle.

Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Abstract: A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command. The controller may program data in a maximum unit of programming for an individual one of the plurality of flash memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract: A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle.

Abstract: A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

Abstract: A system and method for managing program cycles in a multi-layer memory is disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request and an amount of data already programmed in the plurality of memory layers necessary to be programmed in maintenance operations to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the request, and the amount of data already programmed to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle.

Abstract: A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical storage capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical storage capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die, and associated different physical capacity per control line.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met.

Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.