Abstract: The present invention describes immunogenic compositions containing immunogenic polypeptides of African Swine Fever (ASF) virus, including immunogenic compositions containing antigens other than ASF viral antigens, including antigens that may be used in immunization against pathogens that cause diarrheal diseases. Methods of eliciting an immune response with the immunogenic compositions as disclosed and methods of treating an ASF infection are also described.

Abstract: A method is provided for operating a fuel cell stack with improved performance recovery from sub-saturated conditions, the method comprising setting an alert for the performance recovery of the fuel cell stack, performing at least one oxidant starvation by supplying oxidant at a stoichiometric ratio below 1 to the fuel cell stack in at least one pulse for a preset amount of time and at low current while the fuel cell stack does not generate power. The fuel cell system with an improved performance recovery comprises a shorting circuit which is connected to the fuel cell stack at predetermined times (startup, shutdown or standby mode) and an air compressor powered by a DC-DC converter which supplies a predetermined number of oxidant pulses of a predetermined duration to the fuel cell stack.

Abstract: A membrane electrode assembly comprises an anode electrode comprising an anode catalyst layer; a cathode electrode comprising a cathode catalyst layer; and a polymer electrolyte membrane interposed between the anode electrode and the cathode electrode; wherein at least one of the anode and cathode catalyst layers comprises a block co-polymer comprising poly(ethylene oxide) and poly(propylene oxide).

Abstract: The present invention describes immunogenic compositions containing immunogenic polypeptides of African Swine Fever (ASF) virus, including immunogenic compositions containing antigens other than ASF viral antigens, including antigens that may be used in immunization against pathogens that cause diarrheal diseases. Methods of eliciting an immune response with the immunogenic compositions as disclosed and methods of treating an ASF infection are also described.

Abstract: A membrane electrode assembly comprises an anode electrode comprising an anode catalyst layer; a cathode electrode comprising a cathode catalyst layer; and a polymer electrolyte membrane interposed between the anode electrode and the cathode electrode; wherein at least one of the anode and cathode catalyst layers comprises a block co-polymer comprising poly(ethylene oxide) and poly(propylene oxide).

Abstract: A method is provided for operating a fuel cell stack with improved performance recovery from sub-saturated conditions, the method comprising setting an alert for the performance recovery of the fuel cell stack, performing at least one oxidant starvation by supplying oxidant at a stoichiometric ratio below 1 to the fuel cell stack in at least one pulse for a preset amount of time and at low current while the fuel cell stack does not generate power. The fuel cell system with an improved performance recovery comprises a shorting circuit which is connected to the fuel cell stack at predetermined times (startup, shutdown or standby mode) and an air compressor powered by a DC-DC converter which supplies a predetermined number of oxidant pulses of a predetermined duration to the fuel cell stack.

Abstract: A membrane electrode assembly including: an anode electrode; a cathode electrode; and a polymer electrolyte membrane; wherein the cathode includes a first cathode catalyst sublayer including a first precious metal catalyst composition and a first ionomer composition including a first ionomer and a second ionomer; and a second cathode catalyst sublayer including a second precious metal catalyst composition and a second ionomer composition including a third ionomer; wherein the first ionomer is different from the second ionomer in at least one of chemical structure and equivalent weight.

Abstract: A method for external access control to protect system-on-chip (SoC) subsystems and stored subsystem assets is described. The method includes sensing, during a cold boot of an SoC hardware system, a debug fuse vector for access to SoC subsystems of an SoC owner and/or third-party subsystems of an SoC hardware architecture. The method also includes disabling access to each SoC subsystem with a blown fuse in the debug fuse vector. The method further includes re-enabling, by a secure root of trust, access to an SoC subsystem and/or a third-party subsystem for an external debugger when authentication of one or more debug certificates of a third-party owner of the external debugger is successful.

Abstract: A membrane electrode assembly comprises an anode electrode comprising an anode catalyst layer; a cathode electrode comprising a cathode catalyst layer; and a polymer electrolyte membrane interposed between the anode electrode and the cathode electrode; wherein at least one of the anode and cathode catalyst layers comprises a block co-polymer comprising poly(ethylene oxide) and poly(propylene oxide).

Abstract: A membrane electrode assembly including: an anode electrode; a cathode electrode; and a polymer electrolyte membrane; wherein the cathode includes a first cathode catalyst sublayer including a first precious metal catalyst composition and a first ionomer composition including a first ionomer and a second ionomer; and a second cathode catalyst sublayer including a second precious metal catalyst composition and a second ionomer composition including a third ionomer; wherein the first ionomer is different from the second ionomer in at least one of chemical structure and equivalent weight.

Abstract: A membrane electrode assembly comprises an anode electrode comprising an anode gas diffusion layer and an anode catalyst layer; a cathode electrode comprising a cathode gas diffusion layer and a cathode catalyst layer; and a polymer electrolyte membrane interposed between the anode catalyst layer and the cathode catalyst layer; wherein the cathode catalyst layer comprises: a first cathode catalyst sublayer adjacent the polymer electrolyte membrane, the first cathode catalyst sublayer comprising a first catalyst supported on a first carbonaceous support and a second catalyst supported on a second carbonaceous support; and a second cathode catalyst sublayer adjacent the cathode gas diffusion layer, the second cathode catalyst sublayer comprising a third catalyst supported on a third carbonaceous support; wherein the first carbonaceous support is carbon black and the second and third carbonaceous supports are graphitized carbon.

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

Abstract: A membrane electrode assembly comprises an anode electrode comprising an anode gas diffusion layer and an anode catalyst layer; a cathode electrode comprising a cathode gas diffusion layer and a cathode catalyst layer; and a polymer electrolyte membrane interposed between the anode catalyst layer and the cathode catalyst layer; wherein the cathode catalyst layer comprises: a first cathode catalyst sublayer adjacent the polymer electrolyte membrane, the first cathode catalyst sublayer comprising a first catalyst supported on a first carbonaceous support and a second catalyst supported on a second carbonaceous support; and a second cathode catalyst sublayer adjacent the cathode gas diffusion layer, the second cathode catalyst sublayer comprising a third catalyst supported on a third carbonaceous support; wherein the first carbonaceous support is carbon black and the second and third carbonaceous supports are graphitized carbon.

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

Abstract: A system that facilitates interactions between heterogeneous information providers, business process policies, and business process policy objects is provided. The system includes a translation services logic that accepts data format definitions and rules for transforming, translating, converting, reordering, merging, splitting and other operations that adapt one data format to another data format. The translation services logic produces a mapping rule object (MRO) for performing the adaptation(s).

Abstract: A method for managing information technology (IT) through auto discovery analysis to achieve business relevance is provided. An IT infrastructure is monitored to discover managed components of the infrastructure and discover business processes which are supported by the infrastructure. An information model is formed based on the discovered components and the discovered business processes. The information model can be used to provide assorted IT services.

Abstract: A method for infrastructure automatic discovery from business process models through batch processing flows is provided. Data flow in an IT infrastructure is monitored to observe batch processing flows. An information model is formed based on the observed batch processing flows.

Abstract: A method for infrastructure automatic discovery from business process models through middleware flows is provided. Data flow in an infrastructure is monitored to observe middleware flows. An information model is formed based on the observed middleware flows.

Abstract: A system for analyzing business events is provided. The system includes a reactive event processing module, a proactive event processing module and a predictive event processing module. The reactive, proactive and predictive processing modules are each operative to receive and initiate an process associated with a respective type of business event. The system further includes an event delivery module. The event delivery module is operative to deliver the business events to the reactive event processing module, the proactive event processing module and the predictive event processing module.