Patents by Inventor Alastair Mark Boomer

Alastair Mark Boomer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10567214
    Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N?2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 18, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Alastair Mark Boomer, Erich Paul Zwyssig, Gavin Alexander Waite, Willem Zwart
  • Publication number: 20190334756
    Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N?2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Alastair Mark BOOMER, Erich Paul ZWYSSIG, Gavin Alexander WAITE, Willem ZWART
  • Patent number: 7994954
    Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 9, 2011
    Assignee: Wolfson Microelectronics plc
    Inventors: Alastair Mark Boomer, John Paul Lesso
  • Publication number: 20100060498
    Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.
    Type: Application
    Filed: November 17, 2009
    Publication date: March 11, 2010
    Inventors: Alastair Mark Boomer, John Paul Lesso
  • Patent number: 7649480
    Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: January 19, 2010
    Assignee: Wolfson Microelectronics PLC
    Inventors: Alastair Mark Boomer, John Paul Lesso
  • Publication number: 20080129563
    Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 5, 2008
    Inventors: Alastair Mark Boomer, John Paul Lesso