Abstract: An ion-trap chip carrier (10) comprises a generally planar carrier substrate, the substrate having a front surface, a rear surface, and a chip receptacle. A chip support (22) is disposed in the chip receptacle of the carrier substrate, the chip support including at least one generally planar flange (22) extending in or generally parallel to a plane of the carrier substrate, and at least one aperture therein. The chip support comprises a chip receiving zone. The at least one chip support includes at least one front facing electrical terminal (15, 17) in the chip receiving zone, for coupling to a rear facing terminal of an ion-trap chip (50). At least one front facing wire bonding terminal (80, 82) is electrically coupled to the at least one front facing electrical terminal (15, 17), the at least one front facing wire bonding terminal being disposed outside of the chip receiving zone.

Abstract: Alignment features for an optical fibre assembly are formed directly into an ion trap chip to align an optical module with respect to the ion trap chip. This is achieved using microfabrication techniques to etch alignment elements into the surface of the ion trap chip, advantageously carried out with lithographic precision achieving the alignment accuracy required of the optical beam geometries for the application, with an alignment accuracy of a few micrometres. The alignment elements are advantageously etched along defined crystal planes of the silicon substrate of the chip. An external microstructure can be micromachined with lithographic precision to contain locating features that will fit, or “plug”, into the recesses of the chip, for instance ion microtrap chip.

Abstract: An ion-trap chip carrier (10) comprises a generally planar carrier substrate, the substrate having a front surface, a rear surface, and a chip receptacle. A chip support (22) is disposed in the chip receptacle of the carrier substrate, the chip support including at least one generally planar flange (22) extending in or generally parallel to a plane of the carrier substrate, and at least one aperture therein. The chip support comprises a chip receiving zone. The at least one chip support includes at least one front facing electrical terminal (15, 17) in the chip receiving zone, for coupling to a rear facing terminal of an ion-trap chip (50). At least one front facing wire bonding terminal (80, 82) is electrically coupled to the at least one front facing electrical terminal (15, 17), the at least one front facing wire bonding terminal being disposed outside of the chip receiving zone.