Patents by Inventor Albert A. Cooper
Albert A. Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047531Abstract: A metal oxide semiconductor (MOS)-based power device includes a semiconductor region, drain and source electrodes, a gate electrode separated from the semiconductor region by SiO2, where the channel length (CHL) has a range of between about 0.6 ?m and about 0.5 ?m, the silicon dioxide has a corresponding thickness (tox) range of between about 5 nm to about 30 nm, where the CHL has a range of between about 0.5 ?m and about 0.4 ?m, the tox has a corresponding range of between about 5 nm to about 25 nm, where the CHL has a range of between about 0.4 ?m and about 0.3 ?m, the tox has a corresponding range of between about 5 nm to about 20 nm, where the CHL has a range of between about 0.3 ?m and about 0.2 ?m, the tox has a corresponding range of between about 5 nm to about 15 nm.Type: ApplicationFiled: July 30, 2023Publication date: February 8, 2024Applicant: Purdue Research FoundationInventors: James Albert Cooper, Dallas Todd Morisette
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Publication number: 20220384625Abstract: A silicon carbide (SiC) metal oxide semiconductor (MOS) power device is disclosed which includes an SiC drain semiconductor region, an SiC drift semiconductor region coupled to the SiC drain semiconductor region, an SiC base semiconductor region coupled to the SiC drift semiconductor region, an SiC source semiconductor region coupled to the SiC base semiconductor region, a source electrode coupled to the SiC source semiconductor region, a drain electrode coupled to the SiC drain semiconductor region, a gate electrode, wherein voltage of the gate electrode with respect to the SiC base semiconductor region is less than or equal to about 12 V and thickness of the dielectric material is such that the electric field in the dielectric material is about 4 MV/cm when said gate voltage is about 12 V.Type: ApplicationFiled: July 22, 2022Publication date: December 1, 2022Applicant: Purdue Research FoundationInventors: James Albert Cooper, Dallas Todd Morisette, Madankumar Sampath
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Publication number: 20210119042Abstract: A power semiconductor device includes a silicon carbide substrate and has at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The power semiconductor device further includes an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts. Each pit of the pattern of pits has a depth that extends short of the first layer.Type: ApplicationFiled: December 29, 2020Publication date: April 22, 2021Applicant: Global Power Technologies Group, Inc.Inventor: James Albert Cooper, JR.
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Patent number: 10922911Abstract: Embodiments of the present invention provide a system for the use of a collapsible and deployable interactive structure. An interactive structure that is collapsible and deployable is provided in an outdoor or interior location. The interactive structure includes at least a door with a locking mechanism, an interior display, and a physical presence sensor, and may include ceiling tiles made of melt-away material, external displays, and an external bench that houses electrical components. Communication with a user is initiated, and information about the user is obtained for authentication and identification purposes. The user is authenticated, thereby unlocking the door to allow the user to enter the interactive structure. Once the user is inside, the interior display is activated to allow an underlying system to communicate with the user to determine a desired action for with the user. The interior display and underlying system facilitate the performance of the desired action.Type: GrantFiled: December 30, 2019Date of Patent: February 16, 2021Assignee: BANK OF AMERICA CORPORATIONInventors: Jennifer A. Cameron, Maria Cannizzo, Colin Christopherson, Kevin Albert Cooper, Rosemary Hill, Holly Trucco Hillary, Brian Joseph Smith
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Patent number: 10879388Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device includes a stop layer that is disposed at least in part laterally between the pits. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts, wherein the ohmic metal contacts at least parts of the stop layer.Type: GrantFiled: December 5, 2019Date of Patent: December 29, 2020Assignees: Purdue Research Foundation, GLOBAL POWER TECHNOLOGIES GROUPInventor: James Albert Cooper, Jr.
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Publication number: 20200134951Abstract: Embodiments of the present invention provide a system for the use of a collapsible and deployable interactive structure. An interactive structure that is collapsible and deployable is provided in an outdoor or interior location. The interactive structure includes at least a door with a locking mechanism, an interior display, and a physical presence sensor, and may include ceiling tiles made of melt-away material, external displays, and an external bench that houses electrical components. Communication with a user is initiated, and information about the user is obtained for authentication and identification purposes. The user is authenticated, thereby unlocking the door to allow the user to enter the interactive structure. Once the user is inside, the interior display is activated to allow an underlying system to communicate with the user to determine a desired action for with the user. The interior display and underlying system facilitate the performance of the desired action.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Applicant: BANK OF AMERICA CORPORATIONInventors: Jennifer A. Cameron, Maria Cannizzo, Colin Christopherson, Kevin Albert Cooper, Rosemary Hill, Holly Trucco Hillary, Brian Joseph Smith
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Publication number: 20200111904Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device includes a stop layer that is disposed at least in part laterally between the pits. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts, wherein the ohmic metal contacts at least parts of the stop layer.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Global Power Technologies Group, Inc.Inventor: James Albert Cooper, JR.
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Publication number: 20200051127Abstract: Systems and methods are described for authorizing access to resources to entities by representing objects in a graph database. Entities and resources are represented by nodes in the graph, and permissions by edges connecting the nodes. Nodes may be grouped into groupings, the inclusion of a node in a group being represented by an edge. The graph comprises one or more bipartite graphs, such that nodes of one set do not have edges connecting nodes in the set. Navigation of the graph is performed to determine permissions for the entity to access the resources, such as by utilizing edges and inverse edges in the graph to walk a path to the center of the graph, the edges being associated with the permission required to perform the access.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Albert Cooper Johnson, Taylor James White
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Patent number: 10521991Abstract: Embodiments of the present invention provide a system for the use of a collapsible and deployable interactive structure. An interactive structure that is collapsible and deployable is provided in an outdoor or interior location. The interactive structure includes at least a door with a locking mechanism, an interior display, and a physical presence sensor, and may include ceiling tiles made of melt-away material, external displays, and an external bench that houses electrical components. Communication with a user is initiated, and information about the user is obtained for authentication and identification purposes. The user is authenticated, thereby unlocking the door to allow the user to enter the interactive structure. Once the user is inside, the interior display is activated to allow an underlying system to communicate with the user to determine a desired action for with the user. The interior display and underlying system facilitate the performance of the desired action.Type: GrantFiled: August 23, 2018Date of Patent: December 31, 2019Assignee: Bank of America CorporationInventors: Jennifer A. Cameron, Maria Cannizzo, Colin Christopherson, Kevin Albert Cooper, Rosemary Hill, Holly Trucco Hillary, Brian Joseph Smith
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Publication number: 20190386124Abstract: A metal-oxide-semiconductor (MOS) power device includes a drain semiconductor region, a drift semiconductor region coupled to the drain semiconductor region, a base semiconductor region coupled to the drift semiconductor region and isolated by the drift semiconductor region from the drain semiconductor region, a source semiconductor region coupled to the base semiconductor region, a source electrode, a drain electrode, a gate electrode provided adjacent at least a portion of but isolated from the drift semiconductor region by a dielectric material, wherein the dielectric material has a thickness between 1 nm and 30 nm multiplied by a correction factor defined as a ratio of dielectric permittivity of the dielectric material and the permittivity of silicon dioxide, and wherein the device is configured to withstand greater than 100 V between the drain electrode and the source electrode when substantially no current is flowing through the drain electrode.Type: ApplicationFiled: June 11, 2019Publication date: December 19, 2019Applicant: Purdue Research FoundationInventors: James Albert Cooper, Dallas Todd Morisette, Madankumar Sampath
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Patent number: 10504147Abstract: Systems and methods are described for authorizing access to resources to entities by representing objects in a graph database. Entities and resources are represented by nodes in the graph, and permissions by edges connecting the nodes. Nodes may be grouped into groupings, the inclusion of a node in a group being represented by an edge. The graph comprises one or more bipartite graphs, such that nodes of one set do not have edges connecting nodes in the set. Navigation of the graph is performed to determine permissions for the entity to access the resources, such as by utilizing edges and inverse edges in the graph to walk a path to the center of the graph, the edges being associated with the permission required to perform the access.Type: GrantFiled: March 6, 2015Date of Patent: December 10, 2019Assignee: AMAZON TECHNOLOGIS, INC.Inventors: Albert Cooper Johnson, Taylor James White
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Methods of reducing the electrical and thermal resistance of SiC substrates and devices made thereby
Patent number: 10505035Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.Type: GrantFiled: October 2, 2017Date of Patent: December 10, 2019Assignees: Purdue Research Foundation, GLOBAL POWER TECHNOLOGIES GROUPInventor: James Albert Cooper, Jr. -
Patent number: 10491663Abstract: Methods and systems for performing heterogeneous computations on homogeneous input data are disclosed. A plurality of computational specifications are distributed among a plurality of worker nodes. The computational specifications comprise definitions of a plurality of heterogeneous computations. The heterogeneous computations are performed using the worker nodes. Individual ones of the heterogeneous computations are performed based on the set of input data and corresponding ones of the computational specifications, and individual ones of the heterogeneous computations produce respective results. An aggregate result is generated based on the respective results of the heterogeneous computations.Type: GrantFiled: October 28, 2013Date of Patent: November 26, 2019Assignee: Amazon Technologies, Inc.Inventors: Taylor James White, Albert Cooper Johnson
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Patent number: 10268776Abstract: Systems and techniques to access and/or configure information in graph store are provided. In some embodiments, a state table can be generated in addition to a main table, such as a distributed hash table embodying the graph store. The state table can include information indicative of a state of a relationship between a first node and a second node in the graph store. Availability of the state table can permit the control of termination of an update in scenarios of inconsistency and/or concurrent updates. As such, updates to a pair of nodes, each having one or more records, can leverage the state table to access the record(s) of the nodes and to modify an edge associated with the node. The state table also can permit controllably terminating an update and/or ensuring that consistency of the graph store is maintained after the update. Approaches to resolve error during updates to the graph store also are provided.Type: GrantFiled: September 23, 2016Date of Patent: April 23, 2019Assignee: Amazon Technologies, Inc.Inventor: Albert Cooper Johnson
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METHODS OF REDUCING THE ELECTRICAL AND THERMAL RESISTANCE OF SiC SUBSTRATES AND DEVICES MADE THEREBY
Publication number: 20180026132Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.Type: ApplicationFiled: October 2, 2017Publication date: January 25, 2018Inventor: James Albert Cooper, JR. -
Methods of reducing the electrical and thermal resistance of SiC substrates and devices made thereby
Patent number: 9780206Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.Type: GrantFiled: February 29, 2016Date of Patent: October 3, 2017Assignees: Purdue Research Foundation, Global Power Technologies Group, Inc.Inventor: James Albert Cooper, Jr. -
METHODS OF REDUCING THE ELECTRICAL AND THERMAL RESISTANCE OF SiC SUBSTRATES AND DEVICES MADE THEREBY
Publication number: 20170025530Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.Type: ApplicationFiled: February 29, 2016Publication date: January 26, 2017Inventor: James Albert Cooper, JR. -
Patent number: 8607932Abstract: A ladder stabilizing attachment for a ladder is disclosed. The device is basically made of two or more long variable length stabilizing legs FIGS. (1) and (11) attached to the upper part of a ladder by universal joints FIGS. (9) and (9A), and capable of forming a triangular or multi-angular pyramid with the ladder. The legs can be independently positioned to give greater lateral stability, as well reducing slide out tendency of the ladder base. The foot sockets of the stabilizing legs FIG. (5) are designed to minimize overloading and movement due to ladder flexing. The device is constructed so that it can be built into new ladders, and readily adapted for and fitted to most existing ladders.Type: GrantFiled: May 31, 2007Date of Patent: December 17, 2013Inventors: William Albert Cooper, Rosemary Jennings Cooper
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Publication number: 20120225083Abstract: The invention is directed to polypeptides and polypeptide fragments from HIV-1 envelope (Env) proteins following the characterization of Env structures from environments where HIV isolates expose conserved neutralization-sensitive Env structures. There is provided a polypeptide being all or a fragment of an HIV-1 envelope protein from a transmission strain of HIV-1, the polypeptide having neutralization sensitive epitopes that are accessible.Type: ApplicationFiled: September 16, 2009Publication date: September 6, 2012Applicants: THE UNIVERSITY OF MELBOURNE, THE MACFARLANE BURNET INSTITUTE FOR MEDICAL RESEARCH AND PUBLIC HEALTH, NEWSOUTH INNOVATIONS PTY LIMITEDInventors: Damian Purcell, Robert Center, Sharmila Mohana Rama Reddy, Anthony Dominic Kelleher, David Albert Cooper, Paul Rene Gorry, Jasminka Sterjovski
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Patent number: 7294676Abstract: Styrenic resin composition comprising a rubber modified styrene maleic anhydride copolymer and polybutene. The resin is prepared by several methods including adding polybutene into the reactor, or adding polybutene to the syrup exiting the reactor and prior to entering the devolatilizer, or compounding polybutene into the polymer in an extruder after the polymer exits the devolatilizer. The polybutene ranges from 0.1 to 8% by weight and has a number average molecular weight from 900 to 2500. The rubber ranges from 4% to 20% by weight and has a particle size from 0.1 micron to 11 microns. The resin can be extruded into sheet and thermoformed into an article or can be coextruded to produce a laminated article, which may be a container for packaged foods that can be heated in microwave ovens and which container has improved toughness, elongation, and heat distortion resistance properties.Type: GrantFiled: March 24, 2004Date of Patent: November 13, 2007Assignee: NOVA Chemicals Inc.Inventors: John Chi Hee Kwok, Richard Albert Cooper, Steven Michael Krupinski