Abstract: A template for imprint lithography (IL) that reduces significantly template production costs by allowing the same template to be re-used for several technology generations. The template is composed of an array of spaced-apart moveable and individually addressable rods or plungers. Thus, the template can be configured to provide a desired pattern by programming the array of plungers such that certain of the plungers are in an “up” or actuated configuration. This arrangement of “up” and “down” plungers forms a pattern composed of protruding and recessed features which can then be impressed onto a polymer film coated substrate by applying a pressure to the template impressing the programmed configuration into the polymer film. The pattern impressed into the polymer film will be reproduced on the substrate by subsequent processing.

Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).

Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).

Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: Process for fabricating a semiconductor structure (500) comprising depositing a capping layer (67) on a portion (54) of a monocrystalline compound semiconductor layer (66) overlying a template film (64), a monocrystalline perovskite oxide material (60), an amorphous oxide layer (62) and a monocrystalline silicon substrate (52), and then exposing at least one surface region (531) of the single crystal silicon substrate (52) into which a CMOS circuit (56) is formed in a CMOS region (53), followed by heating the CMOS circuit (56) to anneal the CMOS region (53) and, optionally, concurrently transform the monocrystalline perovskite oxide film (60) into an amorphous perovskite oxide film (136). The resulting composite semiconductor structure (500) is also encompassed.

Abstract: Semiconductor structures are provided with high quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates such as large silicon wafers utilizing a compliant substrate. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and an overlying monocrystalline material layer. With laser assisted fabrication, a laser energy source is used to preclean the accommodating buffer layer, to excite the accommodating buffer layer to higher energy to promote two-dimensional growth, and to amorphize the accommodating buffer layer, without requiring transport of the semiconductor structure from one environment to another. When chemical vapor deposition is utilized, the laser radiation source can also be employed to crack volatile chemical precursors and to enable selective deposition.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate includes utilizing an intermetallic layer of an intermetallic compound material.

Abstract: Process for fabricating a semiconductor structure (33), and the resulting structure (33), comprising forming a perovskite oxide film (241) overlying an monocrystalline silicon substrate (22) and an amorphous oxide interface layer (28), which is then surface treated with photonic emissions, such as ultraviolet radiation, effective to eliminate and desorb water at the surface of the perovskite oxide film (241). Subsequently, a monocrystalline compound semiconductor layer (26) is formed overlying the surface-treated perovskite oxide film (241).

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Trenches in composite integrated circuits are provided that may be used for electrical isolation and strain relief. The trenches may also be implemented as optical waveguides to carry optical signals on- or off-chip.

Abstract: Process for fabricating a semiconductor structure (34), and the resulting products, having reduced crystal defects and/or contamination in a monocrystalline compound semiconductor layer (26) that is compliantly attached to a monocrystalline semiconductor substrate (22) via an accommodating buffer layer (36), a capping/template layer (30), and a thin monocrystalline compound semiconductor seed film (38) comprised of a compound semiconductor, in that order from furthest to closest to layer (26).