Patents by Inventor Albert Augustus Burk, Jr.
Albert Augustus Burk, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10541306Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.Type: GrantFiled: September 12, 2012Date of Patent: January 21, 2020Assignee: Cree, Inc.Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, Jr., Anant Kumar Agarwal, Alexander Suvorov
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Patent number: 10403722Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.Type: GrantFiled: September 12, 2012Date of Patent: September 3, 2019Assignee: Cree, Inc.Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, Jr., Anant Kumar Agarwal
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Patent number: 9349797Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.Type: GrantFiled: February 6, 2012Date of Patent: May 24, 2016Assignee: Cree, Inc.Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, Jr., John Williams Palmour
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Patent number: 9054017Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.Type: GrantFiled: January 28, 2013Date of Patent: June 9, 2015Assignee: Cree, Inc.Inventors: Adam William Saxler, Albert Augustus Burk, Jr.
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Publication number: 20140070230Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: CREE, INC.Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, JR., Anant Kumar Agarwal
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Publication number: 20130026493Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.Type: ApplicationFiled: February 6, 2012Publication date: January 31, 2013Applicant: CREE, INC.Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, JR., John Williams Palmour
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Patent number: 8362503Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.Type: GrantFiled: March 9, 2007Date of Patent: January 29, 2013Assignee: Cree, Inc.Inventors: Adam William Saxler, Albert Augustus Burk, Jr.
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Patent number: 8324005Abstract: A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 ?m. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.Type: GrantFiled: October 19, 2010Date of Patent: December 4, 2012Assignee: Cree, Inc.Inventors: Adam William Saxler, Albert Augustus Burk, Jr.
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Publication number: 20110312159Abstract: A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 ?m. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.Type: ApplicationFiled: October 19, 2010Publication date: December 22, 2011Inventors: Adam William Saxler, Albert Augustus Burk, JR.
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Patent number: 7880171Abstract: A bipolar device has at least one p? type layer of single crystal silicon carbide and at least one n? type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.Type: GrantFiled: December 22, 2004Date of Patent: February 1, 2011Assignee: Cree, Inc.Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.
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Patent number: 7825432Abstract: A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 ?m. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.Type: GrantFiled: March 9, 2007Date of Patent: November 2, 2010Assignee: Cree, Inc.Inventors: Adam William Saxler, Albert Augustus Burk, Jr.
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Patent number: 7427326Abstract: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.Type: GrantFiled: November 16, 2006Date of Patent: September 23, 2008Assignee: Cree, Inc.Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.
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Patent number: 6849874Abstract: A bipolar device has at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.Type: GrantFiled: October 26, 2001Date of Patent: February 1, 2005Assignee: Cree, Inc.Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.