Patents by Inventor Albert Birner

Albert Birner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12087830
    Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 10, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Albert Birner, Helmut Brech, John Twynam
  • Publication number: 20240258382
    Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.
    Type: Application
    Filed: February 15, 2024
    Publication date: August 1, 2024
    Inventors: Albert Birner, Helmut Brech, John Twynam
  • Patent number: 11929405
    Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, John Twynam
  • Publication number: 20240030334
    Abstract: In an embodiment, a Group III nitride-based semiconductor device includes: a multilayer Group III nitride-based structure including a first major surface; and a source electrode, a gate electrode and a drain electrode arranged on the first major surface. The gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure includes an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 25, 2024
    Inventors: Helmut Brech, Albert Birner, Michaela Braun, Jan Ropohl, Matthias Zigldrum
  • Patent number: 11869963
    Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: John Twynam, Albert Birner, Helmut Brech
  • Patent number: 11728389
    Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Jan Ropohl
  • Publication number: 20230155000
    Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 18, 2023
    Inventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
  • Patent number: 11581418
    Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 14, 2023
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
  • Publication number: 20220254913
    Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Inventors: John Twynam, Albert Birner, Helmut Brech
  • Publication number: 20220208972
    Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 30, 2022
    Inventors: Albert Birner, Jan Ropohl
  • Patent number: 11342451
    Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies AG
    Inventors: John Twynam, Albert Birner, Helmut Brech
  • Patent number: 11302783
    Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Jan Ropohl
  • Publication number: 20210384318
    Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 9, 2021
    Inventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
  • Publication number: 20210336043
    Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 28, 2021
    Inventors: Albert Birner, Helmut Brech, John Twynam
  • Publication number: 20210336015
    Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 28, 2021
    Inventors: Albert Birner, Helmut Brech, John Twynam
  • Publication number: 20210226039
    Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 22, 2021
    Inventors: Helmut Brech, Albert Birner, John Twynam
  • Patent number: 11031327
    Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 8, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Helmut Brech, Albert Birner
  • Publication number: 20200395447
    Abstract: In an embodiment, a semiconductor device includes a support layer having a first surface configured to support epitaxial growth of at least one Group III nitride, an epitaxial Group III nitride-based multi-layer structure positioned on the first surface of the support layer, and a parasitic channel suppression region positioned at the first surface of the support layer.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 17, 2020
    Inventors: Helmut Brech, Albert Birner, John Twynam
  • Patent number: 10720359
    Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Tobias Herzig
  • Publication number: 20200176594
    Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: John Twynam, Albert Birner, Helmut Brech