Abstract: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.

Abstract: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.

Abstract: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.

Abstract: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.

Abstract: A bipolar device has at least one p?type layer of single crystal silicon carbide and at least one n?type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.

Abstract: A ceiling arrangement for a high temperature epitaxial growth reactor in which silicon carbide epitaxial layers may be grown. The ceiling includes an upper layer of carbon foam and a lower layer of graphite bonded thereto. A support structure for the ceiling is coupled to a nozzle assembly, holding a gas delivering nozzle. The support structure has a lower flange portion which includes an upwardly extending projection defining a knife edge upon which the ceiling rests. The arrangement minimizes unwanted heat transfer from the ceiling to the nozzle assembly and nozzle.

Abstract: A susceptor assembly for use in an epitaxial growth reactor for growing silicon carbide epitaxial layers. The susceptor assembly is rotatable about a central axis and includes a plurality of cavities each for receiving a wafer holder. A plurality of gas passageways leading to respective cavities, carries gas for levitating and rotating the wafer holders in their respective cavities. All of the gas passageways in the susceptor assembly are non-radially oriented.

Abstract: A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.

Abstract: A high Q monolithic metal-insulator-metal (MIM) capacitor utilizing a single crystal dielectric material. A dielectric membrane is epitaxially grown on a substrate. The membrane acts as an etch-stop when a backside etch is used to form a cavity in the substrate, resulting in a single crystal dielectric membrane spanning the cavity. Electrodes are formed on opposite surfaces of the membrane at the cavity location. For a shunt capacitor application, the bottom electrode is connected to the backside substrate metallization. For a series capacitor application, the bottom electrode is isolated from the backside metallization, but is connected to the topside circuitry through a via formed in the membrane. The membrane may consist of two dielectric layers, where the first layer is an etchstop material. In one embodiment the substrate and second dielectric layer are gallium arsenide and the first dielectric layer is aluminum gallium arsenide.