Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: A single chip integrated circuit measuring circuit (1) for determining a characteristic of the impedance of an external complex impedance circuit (2) for facilitating characterization of the impedance of the complex impedance circuit (2) comprises a signal generating circuit (7) for generating a variable frequency stimulus signal for applying to the complex impedance circuit (2). A first receiving circuit (10) receives a response signal from the complex impedance circuit (2) in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter (68) converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter (68) through a first digital output port (14). The response signal from the complex impedance circuit (2) is a current signal, and a current to voltage converter circuit (64) converts the response signal to a voltage signal.

Abstract: A multi-channel circuit (1) comprising a plurality of on-chip channels (CH1 to CH4), each of which comprises a DAC (3) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (11). The analogue output signals from the DACs (3) are outputted on output terminals (7) of the respective channels (CH1 to CH4). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs (3) are inputted to the interface and control logic circuit (11) through an I/O port (10). DAC registers (9) are provided in the respective channels (CH1 to CH4) for storing the digital words to be converted in the corresponding DACs (3). Analogue input terminals (20) are provided for receiving analogue input signals (20), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (3).

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: A multi-channel circuit (1) comprising a plurality of on-chip channels (CH1 to CH4), each of which comprises a DAC (3) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (11). The analogue output signals from the DACs (3) are outputted on output terminals (7) of the respective channels (CH1 to CH4). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs (3) are inputted to the interface and control logic circuit (11) through an I/O port (10). DAC registers (9) are provided in the respective channels (CH1 to CH4) for storing the digital words to be converted in the corresponding DACs (3). Analogue input terminals (20) are provided for receiving analogue input signals (20), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (3).