Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Abstract: Scheduling with split symbols for beam management is described. An apparatus is configured to receive, from a network node, DL signaling including a symbol in a first slot, and to measure a first measurement of a first beam during a first time portion, and a second measurement of a second beam during a second different time portion, of the symbol. The apparatus is configured to communicate, with the network node, using the first or second beam based on at least one of the first measurement or the second measurement. Another apparatus is configured to provide, for a UE, DL signaling including a symbol in a first slot, and to communicate, with the UE, using the first or second beam based on a first and/or second measurement. The first and second measurements are of first and second beams during a first and second different time portions of the symbol, respectively.

Abstract: Aspects of the disclosure are directed to generation of N-port dynamic beams. For example, a user equipment (UE) may be using a 2-port predefined receive beam for communication with a wireless node. The UE may estimate a channel using the predefined receive beam to measure a rank2 reference signal received from the wireless node. The UE may generate a dynamic beam weight to maximize a communication parameter based on the estimated channel. The UE may then apply the dynamic beam weight to an antenna array.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, for a UE beam refinement procedure, a reference signal via a first network node beam. The UE may receive, based at least in part on the UE beam refinement procedure, an indication of a switch to the first network node beam from a second network node beam. Numerous other aspects are described.

Abstract: A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, during a beam management procedure, multiple sets of channel state information reference signals (CSI-RSs). The UE may receive multiple CSI-RSs, wherein one CSI-RS of the multiple CSI-RSs is associated with one set of CSI-RSs of the multiple sets of CSI-RSs, and wherein a beam associated with the one CSI-RS corresponds to a beam associated with the one set of CSI-RSs. The UE may transmit multiple channel quality indicator (CQI) reports based at least in part on the multiple CSI-RSs, wherein one CQI report of the multiple CQI reports is based at least in part on the one CSI-RS of the multiple CSI-RSs. Numerous other aspects are described.

Abstract: Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.

Abstract: Methods and apparatus for beam management where a beam is selected based on an estimated channel correlation matrix. The apparatus determines a channel correlation matrix based on downlink SSB reference signal received at the UE. The apparatus estimates a RSRP of a plurality of beams associated with an uplink channel based on the channel correlation matrix and associated beam weights. The apparatus selects a first beam from the plurality of beams having a highest estimated RSRP for communication with a base station. The apparatus communicates with the base station via the first beam.

Abstract: A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.

Abstract: Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Abstract: A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

Abstract: A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.

Abstract: Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.

Abstract: A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.

Abstract: A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

Abstract: Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

Abstract: A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

Abstract: A technique relates to a circuit. At least one 4 transistor (4T) static random access memory (SRAM) bitcell is included. Each of the 4T SRAM bitcells includes a first PFET, a first NFET, a second PFET, and a second NFET, the first PFET and the first NFET being coupled to form a first output node, and the second PFET and the second NFET being coupled to form a second output node. A pulldown circuit is coupled to the first NFET, the pulldown circuit operable to pull down a voltage at the first output node. A feedback circuit is operable to monitor the first output node, the feedback circuit operable to control the pulldown circuit.