Abstract: Failsafe primary power control apparatus is provided which includes a backside contact of a control relay in series with the power relay which is held open until the initial program load and latch reset is finished. The system also includes a timer which is initiated by a power fault condition signal which is simultaneously applied to the processor. If the processor is capable of handling the fault condition, it puts out a signal which stops the timer. If the processor is not capable of handling the fault, the signal to the timer is not produced and, accordingly, the timer runs the full interval. This causes the backside contact of the control relay to open thus deenergizing the power relay and removing the power from the entire system.