Patents by Inventor Albert Fazio
Albert Fazio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11789641Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: GrantFiled: June 16, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
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Publication number: 20220415892Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: INTEL CORPORATIONInventors: Wilfred Gomes, Abhishek A. Sharma, Conor P. Puls, Mauro J. Kobrinsky, Kevin J. Fischer, Derchang Kau, Albert Fazio, Tahir Ghani
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Publication number: 20220405005Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Applicant: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
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Patent number: 11010061Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.Type: GrantFiled: May 31, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
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Patent number: 10679698Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.Type: GrantFiled: March 28, 2018Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Prashant S. Damle, Wei Fang, Albert Fazio
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Publication number: 20190332278Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.Type: ApplicationFiled: May 31, 2019Publication date: October 31, 2019Applicant: Intel CorporationInventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
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Patent number: 10331360Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.Type: GrantFiled: September 29, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
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Publication number: 20190043571Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.Type: ApplicationFiled: March 28, 2018Publication date: February 7, 2019Inventors: Prashant S. DAMLE, Wei FANG, Albert FAZIO
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Publication number: 20180088834Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Applicant: Intel CorporationInventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
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Patent number: 8649212Abstract: Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.Type: GrantFiled: September 24, 2010Date of Patent: February 11, 2014Assignee: Intel CorporationInventors: Derchang Kau, Albert Fazio
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Patent number: 8291297Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.Type: GrantFiled: December 18, 2008Date of Patent: October 16, 2012Assignee: Intel CorporationInventors: Richard Coulson, Albert Fazio, Jawad Khan
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Publication number: 20120075924Abstract: Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Derchang Kau, Albert Fazio
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Publication number: 20100162084Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: Richard Coulson, Albert Fazio, Jawad Khan
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Patent number: 7465625Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.Type: GrantFiled: October 17, 2006Date of Patent: December 16, 2008Inventors: Been-jon K. Woo, Yudong Kim, Albert Fazio
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Patent number: 7348618Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.Type: GrantFiled: March 30, 2005Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Been-jon K. Woo, Yudong Kim, Albert Fazio
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Publication number: 20070037350Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.Type: ApplicationFiled: October 17, 2006Publication date: February 15, 2007Inventors: Been-jon Woo, Yudong Kim, Albert Fazio
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Publication number: 20060228858Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Inventors: Been-jon Woo, Yudong Kim, Albert Fazio
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Patent number: 7050320Abstract: Briefly, in accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and optionally a memory controller and a storage medium disposed on the integrated circuit where the storage medium includes chalcogenide islands as storage elements. The MEMS layer may include a movable MEMS platform having probes to connect selected chalcogenide islands via positioning of the MEMS platform. A high voltage source disposed external to the memory layer and the MEMS layer may provide a high voltage to a stator electrode on the memory layer and to a rotor electrode on the MEMS platform to control movement of the MEMS platform with respect to the storage medium. The memory device may be utilized in portable electronic devices such as media players and cellular telephones to provide a nonvolatile storage of information.Type: GrantFiled: December 23, 2004Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Stefan Lai, Albert Fazio, Valluri Rao, Mike Brown, Krishnamurthy Murali
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Patent number: 6943071Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.Type: GrantFiled: June 3, 2002Date of Patent: September 13, 2005Assignee: Intel CorporationInventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
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Patent number: RE40567Abstract: A method for determining data stored by a memory cell. The memory cell has a select gate coupled to a wordline, a first electrode coupled to a bitline, and a second electrode coupled to a conductor. The method comprises: floating the bitline; applying a first voltage to the wordline; applying a second voltage to the conductor such that the bitline is set to a third voltage that is equal to the first voltage minus a threshold voltage of the memory cell; and sensing the third voltage to determine the data stored by the memory cell.Type: GrantFiled: February 21, 2002Date of Patent: November 11, 2008Assignee: Intel CorporationInventor: Albert Fazio