Patents by Inventor Albert Frisch
Albert Frisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230034436Abstract: A quantum circuit arrangement with at least one quantum circuit for carrying out a computation on a quantum computer, the quantum circuit arrangement comprising at least a lookup structure being configured for determining a value of a defined function based on a variable represented by a set of qubits, and a binning structure being configured to identify a defined bin based on the variable, wherein the lookup structure is adapted to determine the value of the defined function based on the bin. Further a method implementable on a classical computer for compiling a quantum circuit arrangement with at least one quantum circuit for carrying out a computation on a quantum computer.Type: ApplicationFiled: January 16, 2020Publication date: February 2, 2023Inventors: Albert Frisch, Harry Barowski, Dominik Steenken, David Bucher, Gawel Kus, Isabel Haide, Jan Müggenburg
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Patent number: 11501196Abstract: An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.Type: GrantFiled: November 26, 2018Date of Patent: November 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albert Frisch, Harry Barowski, Markus Brink
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Patent number: 11171142Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.Type: GrantFiled: November 16, 2018Date of Patent: November 9, 2021Assignee: International Business Machines CorporationInventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
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Patent number: 11164879Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.Type: GrantFiled: November 16, 2018Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
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Patent number: 10833089Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.Type: GrantFiled: November 16, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
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Patent number: 10804266Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.Type: GrantFiled: November 16, 2018Date of Patent: October 13, 2020Assignee: International Business Machines CorporationInventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
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Publication number: 20200167684Abstract: An embodiment of a method for qubit tuning includes generating a first magnetic field through a portion of a first layer, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range, the portion of the first layer above a critical temperature. In an embodiment, the method includes cooling the portion of the first layer at least to the critical temperature. In an embodiment, the method includes generating, in response to cooling the portion of the first layer at least to the critical temperature, a second magnetic field to magnetically interact with a qubit of a quantum processor chip such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.Type: ApplicationFiled: November 26, 2018Publication date: May 28, 2020Applicant: International Business Machines CorporationInventors: Albert Frisch, Harry Barowski, Markus Brink
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Publication number: 20200167683Abstract: An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.Type: ApplicationFiled: November 26, 2018Publication date: May 28, 2020Applicant: International Business Machines CorporationInventors: Albert Frisch, Harry Barowski, Markus Brink
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Publication number: 20200161311Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
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Publication number: 20200161312Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
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Publication number: 20200161300Abstract: An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
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Publication number: 20200161310Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Juergen PILLE, Albert FRISCH, Tobias WERNER, Rolf SAUTTER, Dieter WENDEL
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Patent number: 10586006Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: GrantFiled: April 24, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Publication number: 20190251221Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 10318688Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: GrantFiled: March 27, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Publication number: 20180068043Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: March 27, 2017Publication date: March 8, 2018Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Publication number: 20070265209Abstract: A cosmetic or pharmaceutical oil-in-water (o/w) emulsion including an oil phase and a water phase, where at least 40% by weight of the oil phase is a wax component or a mixture of wax components is provided. A cosmetic or pharmaceutical oil-in-water (o/w) emulsion including 15% to 35% by weight of an oil phase which contains 40% to 70% by weight of a mixture of wax components comprising at least one C16-24 fatty alcohol and at least one wax ester of a C12-24 fatty alcohol and a C12-24 fatty acid; 0.5% to 5% by weight of a nonionic alk(en)yl oligoglycoside surfactant; and 50% to 80% by weight water is also provided.Type: ApplicationFiled: December 14, 2006Publication date: November 15, 2007Inventors: Caroline Goget, Ulrich Issberner, Gabriele Strauss, Roland Spoerer, Albert Frisch