Patents by Inventor Albert Gerardus Wilhelmus Philipus van Zuijlen

Albert Gerardus Wilhelmus Philipus van Zuijlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786640
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 10, 2017
    Assignee: Ampleon Netherlands B.V.
    Inventors: Petra Christina Anna Hammes, Josephus Henricus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Publication number: 20160315073
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 27, 2016
    Applicant: Ampleon Netherlands B.V.
    Inventors: Petra Christina Anna Hammes, Josephus Henricus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9406659
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 2, 2016
    Assignee: Ampleon Netherlands B.V.
    Inventors: Petra Christina Anna Hammes, Josephus Henricus Bartholomeus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9190970
    Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: November 17, 2015
    Assignee: NXP B.V.
    Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Publication number: 20150115343
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Inventors: Petra Christina Anna Hammes, Josephus Henricus Bartholomeus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9007129
    Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 14, 2015
    Assignee: NXP, B.V.
    Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
  • Publication number: 20140167858
    Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 19, 2014
    Applicant: NXP B.V.
    Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
  • Publication number: 20140132353
    Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Applicant: NXP B.V.
    Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen