Abstract: An automatic Memory Module sensing and Memory Module address assignment system during an initializing sequence is described. Each Memory Module has a memory assignment register associated therewith, and all memory assignment registers are initialized to an illegal Memory Module address. The interlock and switch signals are sequentially evaluated under control of a scan counter and decoder. A memory assignment counter is utilized to develop sequential Memory Module addresses and is advanced for each Memory Module found to exist in the system. The memory assignment register for the Memory Module under consideration is set to the address specified in the memory assignment counter if the Memory Module is determined to be present, or is left storing the illegal code if the Memory Module being considered is not present in the system or is switched off.