Abstract: A method and apparatus to protect the coded signals sent over physical twisted-pair wiring or between two (2) or more LANs connected by a Wide Area Network (WAN), from unauthorized electronic circuit/wiring monitoring. This is accomplished by varying the assignments of the standard Registered Jack communication pins, varying the transmission speed, inserting meaningless or unrelated data, encrypting data before it is sent or changing network protocol(s) on behalf of the communications adapter/controller of each computer to which it is attached on those LANs.

Abstract: Operationally, the invention transmits a number to a verifiable recipient which indicates to the receiver what the key will be, without sending the key, or some related key. It is an INPUT into a function that takes the inputs to arrive at a completely different key. The idea is that the partial key does not have any resemblance to the final key and does not give the attacker a clue as to what the final key will be, thus, making it far more difficult to find what appears to be a completely unrelated password/key than one that is not obscured. This is also known as using a partial key to transmit a blind key to a verifiable recipient.

Abstract: The present invention provides a simple and efficient cipher and key generation and selection capability from a predetermined, randomly changing, fixed size matrix (N) of ciphers and keys resulting in a very high-order approximation (Nr,c??) of a true One Time Pad for encryption solutions such as the CipherLoc Polymorphic Key Progression Algorithmic Cipher Engine. The ciphers are randomly selected from a pool of user supplied ciphers, FIPS 140-2 or other certified ciphers and the keys are produced from various methods for generating a key that includes reading a data stream from a network or a Cryptographic Pseudo Random Number Generator (CPRNG)/Pseudo Random Number Generator (PRNG) or a Predetermined Cryptographic Key Generator (PCKG) or any combination of all. Ciphers and generated keys are randomly paired and stored in a volatile matrix for use by an encryption solution.

Abstract: Virtual field programmable gate array (VFPGA) duplicates and/or emulates a field programmable gate array through the use of base hardware and firmware that uses RAM as ROM or EPROM and provides control and monitoring and manipulation through the use of elementary and basic device functionality commands (machine code primitives) to accommodate the needs of polymorphic cipher engine software so that the software achieves the same results as thou it had access to programmable logic arrays, gate and logic blocks found in field programmable gate array chips.

Abstract: Virtual field programmable gate array (VFPGA) duplicates and/or emulates a field programmable gate array through the use of base hardware and firmware that uses RAM as ROM or EPROM and provides control and monitoring and manipulation through the use of elementary and basic device functionality commands (machine code primitives) to accommodate the needs of polymorphic cipher engine software so that the software achieves the same results as thou it had access to programmable logic arrays, gate and logic blocks found in field programmable gate array chips.

Abstract: An apparatus and method for monitoring the physical wiring plant of a computer local area network (LAN) in order to detect the presence of extraneous electronic circuitry placed onto that physical wiring which were not originally designed as part of the electronic circuitry of that LAN and reporting the presence of that additional electronic circuitry and taking action against that additional electronic circuitry based on user directive. The LAN asset being monitored could consist of a single device such as a computer, cell phone, credit card machine, network interface card, printer/scanner, server, router, modem, etc. or an entire network of many such devices.

Abstract: The present invention provides a simple and efficient cipher and key generation and selection capability from a predetermined, randomly changing, fixed size matrix (N) of ciphers and keys resulting in a very high-order approximation (Nr,c??) of a true One Time Pad for encryption solutions such as the CipherLoc Polymorphic Key Progression Algorithmic Cipher Engine. The ciphers are randomly selected from a pool of user supplied ciphers, FIPS 140-2 or other certified ciphers and the keys are produced from various methods for generating a key that includes reading a data stream from a network or a Cryptographic Pseudo Random Number Generator (CPRNG)/Pseudo Random Number Generator (PRNG) or a Predetermined Cryptographic Key Generator (PCKG) or any combination of all. Ciphers and generated keys are randomly paired and stored in a volatile matrix for use by an encryption solution.

Abstract: The invention uses a new process called dynamic pin reassignment (DPR) to alter the circuitry. The system assigns input and output signals to buses that lead to a central distribution point, the crossbar, in the circuit. At the crossbar, signals are routed to the appropriate destination over one of the bus wires to the correct chip from the crossbar. At irregular intervals, the signal mapping for each in/out function is changed. The assignments or mappings, comprise the state of the circuit at any time. The period that a state is valid is determined by applying a reseeding function to a portion of a randomized stream that calculates the next state and the duration of validity. Multiple seeds or keys are used to create the states. Because each key changes independently of the other keys and without notice, the time interval for a valid state is greatly reduced, complicating any effort to reveal the internal states of chips.