Patents by Inventor Albert J. Gregoritsch, III

Albert J. Gregoritsch, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer integrated rigid support ring
    Patent number: 7138326
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corp.
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Wafer integrated rigid support ring
    Patent number: 6706621
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing