Abstract: An apparatus for performing an MMX PSADBW instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associated carry bits indicating whether the difference is positive or negative. The apparatus selectively inverts the differences based on the carry bits. Addition logic adds the selectively inverted differences and carry bits substantially in parallel to generate the PSADBW instruction result. In one embodiment, the apparatus also includes two muxes. The first mux selects the selectively inverted differences in the case of a PSADBW instruction and selects a multiply instruction's partial products otherwise. The second mux selects the carry bits in the case of a PSADBW instruction and selects a second multiply instruction's partial products otherwise. The two mux outputs are provided to the addition logic.

Abstract: A pipeline microprocessor that distributes the instruction dispatching function between a main instruction dispatcher and dispatching logic within a plurality of execution units is disclosed. If the main instruction dispatcher requests load data from a data cache that indicates the data is unavailable, the instruction dispatcher provides to the appropriate execution unit the load instruction (without the load data), a tag (also known by the cache) uniquely identifying the unavailable data, and a false data valid indicator. The cache subsequently obtains the data and outputs it on a bus along with the tag. The dispatching logic in the execution unit is monitoring the bus looking for a valid tag that matches tags of entries in its queue with invalid data indicators. Upon a match, the dispatching logic obtains the data from the bus and subsequently dispatches the instruction along with the data to a functional unit for execution.

Abstract: A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register accordingly. A write control unit uses the contents of the status register to control transfers between the MMX register file and the FP register file, so as to only copy those registers that have changed. According to another aspect of the invention, the write control unit insures that architecturally required modifications to the exponent portion of FP registers corresponding to modified MMX registers are provided.

Abstract: An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or MMX instruction was translated and what the instruction type of that previous instruction was by storing the previous instruction type in a register. When the current instruction is translated, the translator compares the current instruction type with the previous instruction type stored in the register to determine if they are different, i.e., if an instruction boundary (a change from MMX to floating point instruction or vice versa) was encountered. If so, the translator generates a signal to indicate that the two register files may be incoherent and need to be made consistent again.

Abstract: A dual register file MMX-type architecture comprises monitoring logic for identifying which registers in a register file have been written to. The monitoring logic is coupled to write-enable logic associated with each register. Detection logic indicates the occurrence of an instruction boundary event and asserts a signal indicating the possibility of data incoherence between the register files. Control logic coupled to the register files cause a transfer of data between the two register files in response to the asserted signal. The monitoring logic acts in conjunction with the write-enable logic to disable write operations to the receiving registers when the corresponding transferring registers have not been written to.

Abstract: An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.

Abstract: An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Abstract: A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.

Abstract: A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit.

Abstract: A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed.

Abstract: A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.

Abstract: A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units.

Abstract: A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer.

Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units.

Abstract: A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit.